HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 623

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Automatic SCI Bit Rate Adjustment
When boot mode is initiated, H8/3048F-ONE measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. H8/3048F-ONE calculates the bit
rate of the transmission from the host from the measured low period, and transmits one H'00 byte
to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment
end indication (H'00) has been received normally, and transmit one H'55 byte to H8/3048F-ONE.
If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above
operations. Depending on the host’s transmission bit rate and H8/3048F-ONE’s system clock
frequency, there will be a discrepancy between the bit rates of the host and H8/3048F-ONE. Set
the host transfer bit rate at 4,800, 9,600 or 19,200 bps * to operate the SCI properly.
Table 18.7 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of H8/3048F-ONE bit rate is possible. The boot program should be executed within
this system clock range.
Table 18.7 System Clock Frequencies for which Automatic Adjustment of H8/3048F-ONE
Note: * Use a host bit rate setting of 4800, 9600, or 19200 bps only. No other setting should be
Host Bit Rate
4800 bps
9,600 bps
19,200 bps
Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
used.
Although the H8/3048F-ONE may also perform automatic bit rate adjustment with bit
rate and system clock combinations other than those shown in table 18.7, a degree of
error will arise between the bit rates of the host and the H8/3048F-ONE, and
subsequent transfer will not be performed normally. Therefore, only combinations of
bit rate and system clock within the ranges shown in table 18.7 can be used for boot
mode execution.
Bit Rate is Possible
Start
bit
System Clock Frequency for Which Automatic Adjustment
of LSI Bit Rate is Possible (MHz)
4 to 25
8 to 25
16 to 25
D0
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
Rev. 3.00 Sep 27, 2006 page 595 of 872
D5
D6
D7
(1 or more bits)
REJ09B0325-0300
High period
Stop
bit