HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 416

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 10 16-Bit Integrated Timer Unit (ITU)
Sample Buffering Setup Procedure
Figure 10.48 shows a sample buffering setup procedure.
Examples of Buffering
Figure 10.49 shows an example in which GRA is set to function as an output compare register
buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match,
and TIOCA and TIOCB are set to toggle at compare match A and B. Because of the buffer setting,
when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA.
This operation is repeated each time compare match A occurs. Figure 10.50 shows the transfer
timing.
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REJ09B0325-0300
Select general register functions
Buffered operation
Set buffer bits
Start counters
Buffering
Figure 10.48 Buffering Setup Procedure (Example)
1
2
3
1.
2.
3.
Set TIOR to select the output compare or input
capture function of the general registers.
Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR
to select buffering of the required general registers.
Set the STR bits to 1 in TSTR to start the timer
counters.