HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 642

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.8.4
While flash memory is being programmed/erased (P bit or E bit in FLMCR1 is set) and the boot
program is executing in the boot mode *
because the programming/erasing have priority.
This is done to avoid the following operation states:
1. Generation of an interrupt during programming/erasing violates the program/erase algorithms
2. Vector-read cannot be carried out normally *
3. If an interrupt is generated during boot program execution, the normal boot mode sequence
With above reasons, there are conditions that exceptionally disable NMI inputs only in the on-
board programming mode. However, this does not assure normal programming/erasing and
microcomputer operation.
Thus, when the flash memory is programmed/erased, all interrupt requests (exception handling
and bus release), including NMI, inside and outside the microcomputer, must be disabled. NMI
interrupt is also disabled in the error-protected state and when the P bit or E bit in FLMCR1 is
retained during flash memory emulation by RAM.
Notes: 1. Indicates the period up to branching to the on-chip RAM boot program area
Rev. 3.00 Sep 27, 2006 page 614 of 872
REJ09B0325-0300
and normal operation can not longer be assured.
programming/erasing and the microcomputer runs away as a result.
cannot be executed.
2. In this case, vector read is not performed normally for the following two reasons:
NMI Input Disable Conditions
(H'FFEF10). (This branch occurs immediately after programming control program
transfer was completed.)
Therefore, after branching to RAM area, NMI input is enabled in states other than the
program/erase state. Thus, interrupt requests inside and outside the microcomputer
must be disabled until initial writing by programming control program (writing of
vector table and NMI processing program, etc.) is completed.
•
•
The correct value cannot be read even by reading the flash memory during
programming/erasing (P bit or E bit in FLMCR1 is set). (Value is undefined.)
If a value has not yet been written to the interrupt vector table, interrupt exception
handling will not be performed correctly.
1
, all interrupts including NMI input must be disabled
2
during interrupt exception handling during