HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 85

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 2 CPU
6. Immediate—#xx:8, #xx:16, or #xx:32
The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as
an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
7. Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction code is sign-extended to 24 bits and added to the 24-bit PC contents to generate a
24-bit branch address. The PC value to which the displacement is added is the address of the first
byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64
words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The
resulting value should be an even number.
8. Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. See figure 2.10. The upper bits of the 8-bit absolute
address are assumed to be 0 (H'0000), so the address range is 0 to 255 (H'000000 to H'0000FF).
Note that the first part of this range is also the exception vector area. For further details see section
5, Interrupt Controller.
Specified by @aa:8
Reserved
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification
Rev. 3.00 Sep 27, 2006 page 57 of 872
REJ09B0325-0300