IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part NumberC8051F023R
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F023R datasheets
 

Specifications of C8051F023R

Core Processor8051Core Size8-Bit
Speed25MHzConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDTNumber Of I /o32
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Ram Size4.25K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Data ConvertersA/D 8x8b, 8x10b; D/A 2x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case64-TQFP, 64-VQFP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Other names336-1035-2  
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C8051F020/1/2/3
16.2. Configuring the External Memory Interface
Configuring the External Memory Interface consists of four steps:
1.
Select EMIF on Low Ports (P3, P2, P1, and P0) or High Ports (P7, P6, P5, and P4).
2.
Select Multiplexed mode or Non-multiplexed mode.
3.
Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or
off-chip only).
4.
Set up timing to interface with off-chip memory or peripherals.
5.
Select the desired output mode for the associated Ports (registers PnMDOUT, P74OUT).
Each of these four steps is explained in detail in the following sections. The Port selection, Multiplexed mode selec-
tion, and Mode bits are located in the EMI0CF register shown in Figure 16.2.
16.3. Port Selection and Configuration
The External Memory Interface can appear on Ports 3, 2, 1, and 0 (C8051F020/1/2/3 devices) or on Ports 7, 6, 5, and
4 (C8051F020/2 devices only), depending on the state of the PRTSEL bit (EMI0CF.5). If the lower Ports are selected,
the EMIFLE bit (XBR2.1) must be set to a ‘1’ so that the Crossbar will skip over P0.7 (/WR), P0.6 (/RD), and if mul-
tiplexed mode is selected P0.5 (ALE). For more information about the configuring the Crossbar, see
“17. PORT INPUT/OUTPUT” on page
The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of
an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port pins reverts to the Port
latches or to the Crossbar (on Ports 3, 2, 1, and 0). See
more information about the Crossbar and Port operation and configuration. The Port latches should be explicitly
configured to ‘park’ the External Memory Interface pins in a dormant state, most commonly by setting them
to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the drivers on
all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output mode of the Port
pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the External Memory Interface oper-
ation, and remains controlled by the PnMDOUT registers. See
for more information about Port output mode configuration.
146
161.
Section “17. PORT INPUT/OUTPUT” on page 161
Section “17. PORT INPUT/OUTPUT” on page 161
Rev. 1.4
Section
for