C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 260

IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part Number
C8051F023R
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F023R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1035-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F023R
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F020/1/2/3
260
Bit7:
Bits6-4:
Bits3-1:
Bit0:
CIDL
R/W
Bit7
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
UNUSED. Read = 000b, Write = don't care.
CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
The minimum high or low time for the ECI input signal is at least 2 system clock cycles.
External oscillator source divided by 8 is synchronized with the system clock.
CPS2
0
0
0
0
1
1
1
1
R/W
Bit6
CPS1
Figure 23.11. PCA0MD: PCA0 Mode Register
0
0
1
1
0
0
1
1
R/W
Bit5
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
-
Timebase
Rev. 1.4
CPS2
R/W
Bit3
(max rate = system clock divided by 4)
High-to-low transitions on ECI
External clock divided by 8
System clock divided by 12
System clock divided by 4
CPS1
R/W
Bit2
Timer 0 overflow
System clock
Reserved
Reserved
CPS0
R/W
Bit1
ECF
R/W
Bit0
SFR Address:
01000000
Reset Value
0xD9

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