IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part NumberC8051F023R
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F023R datasheets
 


Specifications of C8051F023R

Core Processor8051Core Size8-Bit
Speed25MHzConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDTNumber Of I /o32
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Ram Size4.25K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Data ConvertersA/D 8x8b, 8x10b; D/A 2x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case64-TQFP, 64-VQFP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Other names336-1035-2  
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23.3. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of PCA0.
Figure 23.10. PCA0CN: PCA Control Register
R/W
R/W
R/W
CF
CR
-
Bit7
Bit6
Bit5
Bit7:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the Coun-
ter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the CF inter-
rupt service routine. This bit is not automatically cleared by hardware and must be cleared by
software. See “Important Note About the PCA0CN Register” on page 251.
Bit6:
CR: PCA0 Counter/Timer Run Control.
This bit enables/disables the PCA0 Counter/Timer.
0: PCA0 Counter/Timer disabled.
1: PCA0 Counter/Timer enabled.
Bit5:
UNUSED. Read = 0b, Write = don't care.
Bit4:
CCF4: PCA0 Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
Bit3:
CCF3: PCA0 Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
Bit2:
CCF2: PCA0 Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
Bit1:
CCF1: PCA0 Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
Bit0:
CCF0: PCA0 Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
C8051F020/1/2/3
R/W
R/W
R/W
CCF4
CCF3
CCF2
CCF1
Bit4
Bit3
Bit2
Rev. 1.4
R/W
R/W
Reset Value
CCF0
00000000
Bit1
Bit0
SFR Address:
0xD8
(bit addressable)
259