C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 162

IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part Number
C8051F023R
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F023R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1035-2
C8051F020/1/2/3
The C8051F020/1/2/3 devices have a wide array of digital resources which are available through the four lower I/O
Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin
or can be controlled by a digital peripheral or function (like UART0 or /INT1 for example), as shown in Figure 17.2.
The system designer controls which digital functions are assigned pins, limited only by the number of pins available.
This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of
a Port I/O pin can always be read from its associated Data register regardless of whether that pin has been assigned to
a digital peripheral or behaves as GPIO. The Port pins on Port 1 can be used as Analog Inputs to ADC1.
An External Memory Interface which is active during the execution of a MOVX instruction whose target address
resides in off-chip memory can be active on either the lower Ports or the upper Ports. See
DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145
Memory Interface.
The upper Ports (available on C8051F020/2) can be byte-accessed as GPIO pins.
Figure 17.2. Lower Port I/O Functional Block Diagram
2
Highest
UART0
Priority
4
SPI
2
SMBus
2
UART1
6
PCA
2
Comptr.
Outputs
T0, T1,
T2, T2EX,
8
T4,T4EX
/INT0,
/INT1
Lowest
/SYSCLK
Priority
CNVSTR
8
P0
(P0.0-P0.7)
8
P1
(P1.0-P1.7)
Port
8
Latches
P2
(P2.0-P2.7)
8
P3
(P3.0-P3.7)
162
Section “16. EXTERNAL
for more information about the External
XBR0, XBR1,
P0MDOUT, P1MDOUT,
XBR2, P1MDIN
P2MDOUT, P3MDOUT
Registers
Registers
Priority
Decoder
P0
8
I/O
Cells
Digital
P1
Crossbar
8
I/O
Cells
P2
8
I/O
Cells
P3
8
I/O
Cells
To External
To
Memory
ADC1
Interface
Input
(EMIF)
Rev. 1.4
External
Pins
P0.0
Highest
Priority
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
Lowest
Priority
P3.7

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