C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 162
Manufacturer Part Number
IC 8051 MCU 64K FLASH 64TQFP
Silicon Laboratories Inc
Specifications of C8051F023R
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
Program Memory Size
64KB (64K x 8)
Program Memory Type
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
A/D 8x8b, 8x10b; D/A 2x12b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
The C8051F020/1/2/3 devices have a wide array of digital resources which are available through the four lower I/O
Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin
or can be controlled by a digital peripheral or function (like UART0 or /INT1 for example), as shown in Figure 17.2.
The system designer controls which digital functions are assigned pins, limited only by the number of pins available.
This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of
a Port I/O pin can always be read from its associated Data register regardless of whether that pin has been assigned to
a digital peripheral or behaves as GPIO. The Port pins on Port 1 can be used as Analog Inputs to ADC1.
An External Memory Interface which is active during the execution of a MOVX instruction whose target address
resides in off-chip memory can be active on either the lower Ports or the upper Ports. See
DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145
The upper Ports (available on C8051F020/2) can be byte-accessed as GPIO pins.
Figure 17.2. Lower Port I/O Functional Block Diagram
Section “16. EXTERNAL
for more information about the External