UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet
UPSD3433EB40U6
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UPSD3433EB40U6 Summary of contents
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Fast Turbo 8032 MCU with USB and Programmable Logic Features summary ■ Fast 8-bit Turbo 8032 MCU, 40 MHz – Advanced core, 4-clocks per instruction – 10 MIPs peak performance at 40MHz (5V) – JTAG Debug and In-System Programming – ...
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... Note: Operating temperature is in the Industrial range (–40°C to 85°C). 2/293 1st 2nd SRAM Flash Flash ...
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Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 9.5 External Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Connecting external devices to the MCU bus . . . . . . . . . . . . . . . . . . . . . 78 18.4 Programmable bus timing . . . . . ...
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Contents 23.4 Bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 34.7 IN FIFO Pairing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Summary description The Turbo Plus uPSD34xx Series combines a powerful 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal embedded controller. At its core is a fast 4-cycle 8032 ...
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Summary description Figure 2. Block Diagram P3.0:7 P1.0:7 P4.0:7 USB+, USB– 10/293 uPSD34xx (3) 16-bit Timer/ Turbo PFQ Counters 8032 & (2) Core BC External Interrupts UART0 (8) GPIO, Port 3 (8) GPIO, Port 1 (8) 10-bit ...
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Pin descriptions Figure 3. TQFP52 connections PD1/CLKIN JTAG TDO JTAG TDI DEBUG 3.3V V PC2/V JTAG TCK JTAG TMS Note: 1 For 5V applications, V must be connected to a 3.3V source. 2 These signals can be used ...
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Pin descriptions Figure 4. TQFP80 connections PD2/CSI P3.3/TG1/EXINT1 PD1/CLKIN ALE PC7 JTAG TDO JTAG TDI DEBUG PC4/TERR 3. (1) USB+ ( GND USB– PC3/TSTAT PC2/V STBY JTAG TCK (2) SPISEL /PCACLK1/P4.7 (2) SPITXD /TCM5/P4.6 JTAG TMS ...
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Table 2. Pin definitions Signal 80-Pin Port Pin Name No. MCUAD0 AD0 36 MCUAD1 AD1 37 MCUAD2 AD2 38 MCUAD3 AD3 39 MCUAD4 AD4 41 MCUAD5 AD5 43 MCUAD6 AD6 45 MCUAD7 AD7 47 T2 P1.0 52 ADC0 T2X ...
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Pin descriptions Table 2. Pin definitions Signal 80-Pin Port Pin Name No. P3.0 RxD0 75 P3.1 TXD0 77 EXINT0 P3.2 79 TGO P3.3 INT1 P3.6 SDA 44 P3.7 SCL 46 T2 P4.0 33 ...
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Table 2. Pin definitions Signal 80-Pin Port Pin Name No. PSEN 63 ALE 4 RESET_IN 68 XTAL1 48 XTAL2 49 DEBUG 8 PA0 35 PA1 34 PA2 32 PA3 28 PA4 26 PA5 24 PA6 22 PA7 21 PB0 ...
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Pin descriptions Table 2. Pin definitions Signal 80-Pin Port Pin Name No. JTAGTDI TDI 7 JTAGTDO TDO 6 PC7 5 PD1 CLKIN 3 PD2 CSI 1 USB+ 11 USB– 14 3.3V 3.3V ...
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Hardware description The uPSD34xx has a modular architecture built from a stacked die process. There are two die, one is designated “MCU Module” in this document, and the other is designated “PSD Module” (see Figure 5 on page ...
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Hardware description Figure 5. Functional modules Port 3 - UART0, Intr, Timers Port Clock Unit Dual UARTs Interrupt Dedicated Memory Interface Prefetch, Branch Cache 8-Bit/16-Bit Die-to-Die Bus Enhanced MCU Interface PSD Page Register Decode PLD uPSD34xx 18/293 ...
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Memory organization The 8032 MCU core views memory on the MCU module as “internal” memory and it views memory on the PSD module as “external” memory, see Internal memory on the MCU Module consists of DATA, IDATA, and ...
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Memory organization 4.1 Internal memory (MCU module, standard 8032 memory: DATA, IDATA, SFR) 4.1.1 DATA memory The first 128 bytes of internal SRAM ranging from address 0x0000 to 0x007F are called DATA, which can be accessed using 8032 direct or ...
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Program memory External program memory is addressed by the 8032 using its 16-bit Program Counter (PC) and is accessed with the 8032 signal, PSEN. Program memory can be present at any address in program space between 0x0000 and ...
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Memory organization Flash memory back to program space when finished. See the VM Register page 197) in the PSD Module section of this document for more details. 22/293 uPSD34xx (Table 104 on ...
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MCU core performance enhancements Before describing performance features of the uPSD34xx, let us first look at standard 8032 architecture. The clock source for the 8032 MCU creates a basic unit of timing called a machine-cycle, which is ...
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MCU core performance enhancements Figure 8. Instruction Pre-Fetch Queue and Branch Cache Branch Cache (BC) Instruction Byte 16-bit Program Memory Instruction Byte on PSD Module 5.1 Pre-fetch queue (PFQ) and branch cache (BC) The PFQ is always working to ...
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MCU clocks). But it is also important to understand PFQ operation on multi-cycle instructions. 5.2 PFQ example, multi-cycle instructions Let us look at a string of two-byte, two-cycle instructions in three instructions executed sequentially in this example, instructions ...
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MCU core performance enhancements Figure 10. uPSD34xx multi-cycle instructions compared to standard 8032 A1 A2 uPSD34xx Std 8032 Byte 1 26/293 Three 2-byte, 2-cycle Instructions, uPSD34xx vs. Standard 8032 24 Clocks Total (4 clocks per cycle) Inst A B1 ...
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MCU module description This following sections provide a detailed description of the MCU Module system functions and peripherals, including: ● 8032 MCU Registers ● Special Function Registers ● 8032 Addressing Modes ● uPSD34xx Instruction Set Summary ● Dual ...
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MCU registers 7 8032 MCU registers The uPSD34xx has the following 8032 MCU core registers, also shown in Figure 11. 8032 MCU registers 7.1 Stack pointer (SP) The 8-bit register which holds the current location of ...
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B Register to hold 16-bit operands. The ACC is referred to as “A” in the MCU instruction set. 7.5 B register (B) The B Register is a general purpose 8-bit register for temporary data storage and also used ...
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MCU registers by-zero condition. The OV flag is cleared by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. The CLRV instruction will clear the OV flag at any time. 7.7.6 Parity flag (P) The P ...
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Special function registers (SFR) A group of registers designated as Special Function Register (SFR) is shown in page 32. SFRs control the operating modes of the MCU core and also control the peripheral interfaces and I/O pins on ...
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Special function registers (SFR) CAPCOML4, CAPCOMH4, TCMMODE4, CAPCOML5, CAPCOMH5, TCMMODE5, PWMF0, PMWF1 ● SPI interface registers SPICLKD, SPISTAT, SPITDR, SPIRDR, SPICON0, SPICON1 2 ● interface registers S1SETUP, S1CON, S1STA, S1DAT, S1ADR ● Analog to Digital Converter registers ACON, ...
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Table 5. SFR memory map with direct address and reset value ADCPS – – 95 ADAT0 96 ADAT1 – – 97 ACON AINTF AINTEN SM0 SM1 (1) 98 SCON0 <9Fh> <9Eh> 99 SBUF0 ...
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Special function registers (SFR) Table 5. SFR memory map with direct address and reset value 7 6 CAPCO AF ML1 P3.7 P3.6 ( <B7h> <B6h> CAPCO B1 MH1 CAPCO B2 ML2 CAPCO B3 MH2 B4 PWMF0 B5 B6 ...
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Table 5. SFR memory map with direct address and reset value 7 6 CAPCO C1 ML3 CAPCO C2 MH3 CAPCO C3 ML4 CAPCO C4 MH4 CAPCO C5 ML5 CAPCO C6 MH5 C7 PWMF1 TF2 EXF2 (1) C8 T2CON <CFh> ...
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Special function registers (SFR) Table 5. SFR memory map with direct address and reset value S1SETU DB SS_EN P DC S1CON CR2 EN1 DD S1STA GC STOP DE S1DAT DF S1ADR ( <bit addresses: E7h, ...
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Table 5. SFR memory map with direct address and reset value CCON0 PLLM[4] PLLEN FA CCON1 FB CCON2 – – FC CCON3 – – Note: 1 This SFR can ...
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The 8032 MCU uses 11 different addressing modes listed below: ● Register ● Direct ● Register Indirect ● Immediate ● External Direct ● External Indirect ● Indexed ● Relative ● Absolute ● Long ...
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Immediate Addressing This mode uses 8-bits of data (a constant) contained in the second byte of the instruction, and stores it into the memory location or register indicated by the first byte of the instruction. Thus, the data ...
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PC or DPTR value to the contents of the accumulator. The value in the accumulator is referred index. The data fetched from the final location in program memory is stored ...
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A8h, so each of the eight bits in IE can be addressed individually at address A8h, A9h, ...up to AFh.) For example: SETB AFh ; Set the individual EA bit (Enable All ; Interrupts) inside the SFR ...
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Tables 6 through number of bytes and number of machine cycles required to implement each instruction. This is the standard 8051 instruction set. The meaning of “machine cycles” is how many ...
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Mnemonic and Use INC DPTR MUL AB DIV Note: 1 All mnemonics copyrighted ©Intel Corporation 1980. Table 7. Logical instruction set (1) Mnemonic and Use ANL A, Rn ANL A, direct ANL A, @Ri ANL ...
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Table 8. Data transfer instruction set (1) Mnemonic and Use MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, ...
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Table 9. Boolean variable manipulation instruction set (1) Mnemonic and Use CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV ...
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Mnemonic and Use @Ri, #data, CJNE rel DJNZ Rn, rel DJNZ direct, rel Note: 1 All mnemonics copyrighted ©Intel Corporation 1980. Table 11. Miscellaneous instruction set (1) Mnemonic and Use NOP Note: 1 All mnemonics ...
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Dual data pointers XDATA is accessed by the External Direct addressing mode, which uses a 16-bit address stored in the DPTR Register. Traditional 8032 architecture has only one DPTR Register. This is a burden when transferring data between ...
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Dual data pointers 11.2 Data pointer mode register, DPTM (86h) The two “background” data pointers, DPTR0 and DPTR1, can be configured to automatically increment, decrement, or stay the same after a MOVX instruction accesses the DPTR Register. Only the currently ...
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LOOP: MOVX MOVX (1) DJNZ MOV MOV Note: 1 The code loop where the data transfer takes place is only 3 lines of code. (1) A, @DPTR ; load XDATA byte from source into ACC. ; after load completes, ...
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Debug unit 12 Debug unit The 8032 MCU Module supports run-time debugging through the JTAG interface. This same JTAG interface is also used for In-System Programming (ISP) and the physical connections are described in the PSD Module section, page 251. ...
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V CC module on page – The duration of a pulse, generated when the Event pin configured as an output, is one MCU clock cycle. This is an active-low signal, so the first edge when an event ...
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Interrupt system 13 Interrupt system The uPSD34xx has an 12-source, two priority level interrupt structure summarized in Table 16. Firmware may assign each interrupt source either high or low priority by writing to bits in the SFRs named, IP and ...
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If an interrupt flag is not cleared after servicing the interrupt, an unwanted interrupt will occur upon exiting the ISR. After the interrupt is serviced, the last instruction executed by the ISR is RETI. The RETI informs the MCU ...
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Interrupt system Interrupt Polling Source Priority PCA 11 UART1 12 (low) 004Bh Note: 1 See USB interrupt flag registers UIF0-3. Figure 13. Enabling and polling interrupts Interrupt Sources Reserved 54/293 Flag Bit Name (SFR.bit Flag Bit position) Vecto Cleared 1 ...
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Individual interrupt sources 13.1.1 External interrupts Int0 and Int1 External interrupt inputs on pins EXTINT0 and EXTINT1 (pins 3.2 and 3.3) are either edge- triggered or level-triggered, depending on bits IT0 and IT1 in the SFR named TCON. ...
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Interrupt system 13.1.8 PCA interrupt The PCA has eight interrupt sources, which are logically ORed together when interrupting the MCU.The ISR must read the flag bits to determine the cause of the interrupt. ● Each of the six TCMs can ...
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Table 18. IEA: Interrupt Enable Addition Register (SFR A7h, reset value 00h) Bit 7 Bit 6 EADC ESPI Bit Symbol (1) 7 EADC (1) 6 ESPI (1) 5 EPCA (1) 4 ES1 3 – 2 – ( ...
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Interrupt system Table 20. IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h) Bit 7 Bit 6 PADC PSPI Bit Symbol (1) 7 PADC (1) 6 PSPI (1) 5 PPCA (1) 4 PS1 3 – 2 – (1) 1 ...
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MCU clock generation Internal system clocks generated by the clock generation unit are derived from the signal, XTAL1, shown in external crystal or oscillator device. The SFR named CCON0 the clock generation unit. There are two clock signals ...
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MCU clock generation 14.2.2 USB_CLK The uPSD34xx has a dedicated analog phase locked loop (PLL) that can be configured to generate the 48MHz USB_CLK clock on a wide range of f must be at 48MHz for the USB to function ...
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Figure 14. Clock Generation Logic PCON[1]: PD, Power-Down Mode XTAL1 (f OSC ) PCON[1] CCON0[6] CCON[2:0], PCON[0]: IDL, Clock Pre-Scaler Select 3 XTAL1 (default) 0 XTAL1 / XTAL1 / XTAL1 / ...
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MCU clock generation Table 22. CCON0: Clock Control Register (SFR F9h, reset value 50h) Bit 7 Bit 6 PLLM[4] PLLEN Bit Symbol 7 PLLM[4] 6 PLLEN 5 UPLLCE 4 DBGCE 3 CPUAR 2:0 CPUPS Table 23. CCON1 PLL Control Register ...
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Power saving modes The uPSD34xx is a combination of two die, or modules, each module having its own current consumption characteristics. This section describes reduced power modes for the MCU Module. See Section 28.1.16: Power management on page ...
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Power saving modes 15.2 Power-down Mode Power-down Mode will halt the 8032 core and all MCU peripherals (Power-down Mode blocks MCU_CLK, USB_CLK, and PERIPH_CLK). This is the lowest power state for the MCU Module. When the PSD Module is also ...
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Table 24. MCU Module Port and Peripheral Status during Reduced Power Modes Mode Ports Maintain Idle Data Power- Maintain down Data Note: 1 The Watchdog Timer is not active during Idle Mode. Other supervisor functions are ...
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Power saving modes Table 26. PCON: Power Control Register (SFR 87h, reset value 00h) Bit 7 Bit 6 SMOD0 SMOD1 Bit Symbol 7 SMOD0 6 SMOD1 5 – 4 POR 3 RCLK1 2 TCLK1 IDL 66/293 Bit ...
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Oscillator and external components The oscillator circuit of uPSD34xx devices is a single stage, inverting amplifier in a Pierce oscillator configuration. The internal circuitry between pins XTAL1 and XTAL2 is basically an inverter biased to the transfer point. ...
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Oscillator and external components Figure 15. Oscillator and clock connections XTAL1 (in) C1 Ceramic Resonator Crystal, fundamental mode (3-40MHz) Crystal, overtone mode (25-40MHz) 68/293 XTAL2 (out) XTAL C2 (f OSC ) XTAL (f OSC ) ...
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I/O ports of mcu module The MCU Module has three 8-bit I/O ports: Port 1, Port 3, and Port 4. The PSD Module has four other I/O ports: Port and D. This section describes only ...
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I/O ports of mcu module 17.1.1 GPIO function Ports in GPIO mode operate as quasi-bidirectional pins, consistent with standard 8051 architecture. GPIO pins are individually controlled by three SFRs: ● SFR, P1 (Table 27 on page ● SFR, P3 (Table ...
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CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All other types of reads to port SFRs will read the actual pin logic level and not the port latch. This is consistent with 8051 architecture. Figure 16. MCU module port ...
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I/O ports of mcu module Figure 18. MCU I/O cell block diagram for port 3 Enable_I Select_Alternate_Func Digital_Alt_Func_Data_Out P3.X SFR Read Latch (for R-M-W instructions) MCU_Reset 8032 Data Bus Bit GPIO P3.X SFR Write Latch P3.X SFR Read Pin Digital_Pin_Data_In ...
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Table 27. P1: I/O port 1 register (SFR 90h, reset value FFh) Bit 7 Bit 6 P1.7 P1.6 Bit Symbol 7 P1.7 6 P1.6 5 P1.5 4 P1.4 3 P1.3 2 P1.2 1 P1.1 0 P1.0 Note: 1 Write ...
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I/O ports of mcu module Table 29. P4: I/O Port 4 Register (SFR C0h, reset value FFh) Bit 7 Bit 6 P4.7 P4.6 Bit Symbol 7 P4.7 6 P4.6 5 P4.5 4 P4.4 3 P4.3 2 P4.2 1 P4.1 0 ...
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Only the low-side driver and the internal weak pull-ups are used. Only Port 3 supports open-drain mode an external pull-up resistor on each bus signal, typically 4.7KΩ the alternate function is PCA ...
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I/O ports of mcu module Table 32. P1SFS1: Port 1 Special Function Select 1 Register (SFR 8Fh, reset value 00h) Bit 7 Bit 6 P1SF17 P1SF16 Table 33. P1SFS0 and P1SFS1 Details Port 1 Pin R/W 0 R,W 1 R,W ...
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Table 36. P4SFS0 and P4SFS1 Details Port 4 Pin R/W 0 R,W 1 R,W 2 R,W 3 R,W 4 R,W 5 R,W 6 R,W 7 R,W Alternate 1 Port Default Port Function Function P4SFS0[ P4SFS0[ ...
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MCU bus interface 18 MCU bus interface The MCU Module has a programmable bus interface which is a modified 8032 bus with 16 multiplexed address and data lines. The bus supports four types of data transfer (16 bit), ...
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A[10:8] and the remaining pins can be configured for other functions such as generating chip selects to the external devices. Figure 20. Connecting external devices using ports A and B for address AD[15:0] MCU Module AI10434 Figure 21. Connecting ...
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MCU bus interface It is not possible to specify in the BUSCON Register a different number of MCU_CLK periods for various address ranges. For example, the user cannot specify 4 MCU_CLK periods for RD read cycles to one address range ...
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Table 37. BUSCON: bus control register (SFR 9Dh, reset value EBh) Bit 7 Bit 6 EPFQ EBC Bit Symbol 7 EPFQ 6 EBC 5:4 WRW[1:0] 3:2 RDW[1:0] 1:0 CW[1:0] Bit 5 Bit 4 Bit 3 WRW[1:0] RDW[1:0] R/W Enable ...
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MCU bus interface Table 38. Number of MCU_CLK Periods Required to Optimize Bus Transfer Rate MCU Clock Frequency, MCU_CLK (f 40MHz, Turbo mode PSD 40MHz, Non-Turbo mode PSD 36MHz, Turbo mode PSD 36MHz, Non-Turbo mode PSD 32MHz, Turbo mode PSD ...
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Supervisory functions Supervisory circuitry on the MCU Module will issue an internal reset signal to the MCU Module and simultaneously to the PSD Module as a result of any of the following four events: ● The external RESET_IN ...
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Supervisory functions 19.2 Low V voltage detect, LVD CC An internal reset is generated by the LVD circuit when After V LV_THRESH asserted for t RST_ACTV disabled by SFR), even in Idle Mode and Power-down Mode. The ...
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To prevent the WDT from timing out and generating a reset, firmware must repeatedly write some value to WDRST before the count reaches FFFFFh. Whenever WDRST is written, the upper 8 bits of the 24-bit counter are loaded with ...
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Supervisory functions In this example 100ns (4 MCU_CLK periods x 25ns) MACH_CYC N OVERFLOW WDT PERIOD The actual value will be slightly longer due to PFQ/BC. 19.5.1 Firmware Example: The following 8051 assembly code illustrates how to operate ...
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Standard 8032 timer/counters There are three 8032-style 16-bit Timer/Counter registers (Timer 0, Timer 1, Timer 2) that can be configured to operate as timers or event counters. There are two additional 16-bit Timer/Counters in the Programmable Counter Array ...
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Standard 8032 timer/counters period ( OSC, sample period must be calculated based on the resultant, longer, MCU_CLK frequency. In this case, an external clock signal on pins C0, C1 should have a duration longer than one ...
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SFR, TMOD Timer 0 and Timer 1 have four modes of operation controlled by the SFR named TMOD (Table 42). 20.5 Timer 0 and Timer 1 operating modes The “Timer” or “Counter” function is selected by the C/T ...
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Standard 8032 timer/counters turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator fact, in any application not requiring ...
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Figure 25. Timer/counter mode 0: 13-bit counter f OSC C1 pin Gate EXTINT1 pin Figure 26. Timer/counter mode 2: 8-bit Auto-reload f OSC C1 pin Gate EXTINT1 pin Figure 27. Timer/counter mode 3: two 8-bit counters f OSC C0 ...
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Standard 8032 timer/counters 20.6.1 Capture mode In Capture Mode there are two options which are selected by the bit EXEN2 in T2CON. Figure 28 on page 97 If EXEN2 = 0, then Timer 16-bit timer if C/T2 ...
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Table 43. T2CON: Timer 2 control register (SFR C8h, reset value 00h) Bit 7 Bit 6 TF2 EXF2 Bit Symbol 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2 0 CP/RL2 Note: 1 The ...
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Standard 8032 timer/counters Table 44. Timer/Counter 2 Operating Modes Bits in T2CON SFR RCLK Mode or TCLK 0 16-bit Auto- reload 0 0 16-bit Capture 0 Baud 1 Rate Generato 1 r Off x ↓ Note: = falling edge 20.6.3 ...
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The timer can be configured for either “timer” or “counter” operation. In the most typical applications configured for “timer” operation (C/T2 = 0). “Timer” operation is a little different for Timer 2 when it's being used as ...
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Standard 8032 timer/counters Table 45. Commonly used baud rates generated from timer2 (T2CON = 34h) f MHz OSC Baud Rate 40.0 40.0 40.0 40.0 40.0 36.864 36.864 36.864 36.864 36.864 36.0 36.0 36.0 24.0 24.0 24.0 24.0 12.0 12.0 11.0592 ...
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Figure 28. Timer 2 in capture mode f ÷ 12 OSC T2 pin Transition Detector T2X pin Figure 29. Timer 2 in auto-reload mode f ÷ 12 OSC T2 pin Transition Detector T2X pin C/ TL2 (8 ...
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Standard 8032 timer/counters Figure 30. Timer 2 in baud rate generator mode Note: Oscillator frequency is divided by 2, not 12 like in other timer modes. f ÷ 12 OSC T2 pin Transition Detector T2X pin Note: Availability of additional ...
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Serial UART interfaces uPSD34xx devices provide two standard 8032 UART serial ports. – The first port, UART0, is connected to pins RxD0 (P3.0) and TxD0 (P3.1) – The second port, UART1 is connected to pins RxD1 (P1.2) and ...
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Serial UART interfaces 21.1.3 Mode 2 Mode 2 provides asynchronous, full-duplex communication using a total of 11 bits per data byte. Data is transmitted through TxD and received through RxD with: a Start Bit (logic '0'); eight data bits (LSB ...
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SM2 has no effect in Mode 0, and in Mode 1, SM2 can be used to check the validity of the stop bit Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated ...
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Serial UART interfaces Table 48. SCON1: serial port UART1 control register (SFR D8h, reset value 00h) Bit 7 Bit 6 SM0 SM1 Bit Symbol 7 SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 ...
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Using timer 1 to generate baud rates When Timer 1 is used as the baud rate generator (bits RCLK = 0, TCLK = 0), the baud rates in Modes 1 and 3 are determined by the Timer 1 ...
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Serial UART interfaces UART Mode f OSC Modes 3.6864 Modes 3.6864 Modes 1.8432 Modes 1.8432 21.4 More about UART mode 0 Refer to the block diagram in page ...
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Figure 31. UART mode 0, block diagram Write to SBUF f OSC /12 REN R1 Figure 32. UART Mode 0, Timing Diagram Write to SBUF Send Shift RxD (Data Out) TxD (Shift Clock) TI Write to SCON RI Receive ...
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Serial UART interfaces of the MCU the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the writing of SBUF. Transmission begins with activation of SEND which ...
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Figure 33. UART Mode 1, Block Diagram Timer1 Timer2 Overflow Overflow ÷ SMOD 0 1 TCLK 0 1 RCLK Figure 34. UART Mode 1, Timing Diagram Tx Clock Write to SBUF Send Data Shift TxD TI Rx ...
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Serial UART interfaces 21.6 More About UART Modes 2 and 3 For Mode 2, refer to the block diagram in Figure 36 on page and timing diagram in Keep in mind that the baud rate is programmable to either 1/32 ...
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Figure 35. UART Mode 2, Block Diagram f OSC /32 ÷ SMOD Figure 36. UART Mode 2, Timing Diagram Tx Clock Write to SBUF Send Data Shift TxD TI Stop Bit Generator Rx Clock RxD Bit Detector ...
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Serial UART interfaces Figure 37. UART Mode 3, Block Diagram Timer1 Timer2 Overflow Overflow ÷ SMOD 0 1 TCLK 0 1 RCLK Figure 38. UART Mode 3, Timing Diagram Tx Clock Write to SBUF Send Data Shift TxD ...
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IrDA interface uPSD34xx devices provide an internal IrDA interface that will allow the connection of the UART1 serial interface directly to an external infrared transceiver device. The IrDA interface does this by automatically shortening the pulses transmitted on ...
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IrDA interface The UART1 serial channel can operate in one of four different modes as shown in on page 100 in Section 21: Serial UART interfaces on page used for IrDA communication, UART1 must operate in Mode 1 only, to ...
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Table 51. Baud rate selection register (SFR xxh, reset value xxh) Bit Symbol 7:4 BR[3:0] 3:2 PULSE 1:0 IRDAEN Table 52. Baud rate of UART#1 for IrDA interface BR3 ...
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IrDA interface To produce this fixed data pulse width when the PULSE bit = 0, a prescaler is needed to generate an internal reference clock, SIRClk, shown in derived by dividing the oscillator clock frequency, f SFR named IRDACON. A ...
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I C interface uPSD34xx devices support one serial I channel, having a bi-directional data signal (SDA, pin P3.6) and a clock signal (SCL, pin P3.7) based on open-drain line drivers, requiring external pull-up resistors, R typical value ...
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I C interface 23.2 Communication flow data flow control is based on the fact that all I lines with open-drain (or open-collector) line drivers pulled up with external resistors, creating a wired-AND situation. This means that ...
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A few things to know related to these transfers: ● Either the Master or Slave device can hold the SCL clock line low to indicate it needs more time to handle a byte transfer. An indefinite holding period is ...
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I C interface The interface may operate as either a Master or a Slave within a given application, controlled by firmware writing to SFRs. By default after a reset, the I SCL/P3.7 pins default to GPIO input mode, high ...
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General call address A General Call (GC) occurs when a Master-Transmitter initiates a transfer containing a Slave address of 0000000b, and the R/W bit is logic 0. All Slave devices capable of responding to this broadcast message will ...
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I C interface 2 Figure 43 interface SIOE block diagram SCL / P3.7 SDA / P3.6 AI09626 120/293 Open- Arbitration Input Drain Output Generation Open- Serial DATA IN Drain Input Output Shift Direction Serial DATA OUT b7 ...
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I C interface control register (S1CON) Table 54. Serial control register S1CON (SFR DCh, reset value 00h) Bit 7 Bit 6 CR2 ENI1 Bit Symbol 7 CR2 6 ENI1 5 STA 4 STO 3 ADDR 2 AA ...
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I C interface Table 55. Selection of the SCL Frequency in Master Mode based on f CR2 CR1 Note: 1 These values are ...
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Table 56. S1STA: I Bit 7 Bit 6 GC STOP Bit Symbol STOP 5 INTR 4 TX_MODE 3 BBUSY 2 BLOST 1 ACK_RESP 0 SLV 2 C interface status register (SFR DDh, reset value 00h) Bit ...
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I C interface 2 23. data shift register (S1DAT) The S1ADR register serial byte that has just been received. The MCU may access S1DAT while the SIOE is not in the process of shifting a byte (the ...
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I C START sample setting (S1SETUP) The S1SETUP register will be sampled before the SIOE validates the START condition, giving the SIOE the ability to reject noise or illegal transmissions. Because the minimum duration of an START ...
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I C interface Table 60. Number of I Condition) Contents of S1SETUP SS_EN bit ... 1 1 ... 1 Table 61. Start condition hold time Bus Speed Standard Fast High Note: 1 ...
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Table 62. S1SETUP examples for various Bus Speed, Parameter f SCL Recommended S1SETUP Value Number of Samples Standard Time Between Samples Total Sampled Period Recommended S1SETUP Value Number of Samples Fast Time Between Samples Total ...
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I C interface Set I2C clock prescaler to determine fSCL – SFR S1CON.CR[2:0] = desired SCL freq. Set bus START condition sampling – SFR S1SETUP[7:0] = number of samples Enable individual I2C interrupt and set priority – SFR IEA.I2C ...
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Set global variables to indicate Master-Xmitter – I2C_master = 1, I2C_xmitter = 0 Disable Master from returning an ACK – SFR S1CON. Enable I2C SIOE – SFR S1CON.INI1 = 1 Transmit Address and R/W bit = 1 ...
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I C interface Enable All Interrupts and go do something else – SFR IE. 23.13.1 Interrupt service routine (ISR typical I C interrupt service routine would handle a interrupt for any of the four combinations ...
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Else If mode is Master-Receiver: Bus Arbitration lost? (status.BLOST=1?) If Yes, Arbitration was lost: – S1DAT = dummy, write to release bus – Exit ISR, SIOE will switch to Slave Recv mode If No, Aribitration was not lost, continue: ...
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I C interface Is this the next to last byte to receive from Slave? If this is the next to last byte, do not allow Master to ACK on next interrupt. – S1CON. don’t let Master return ...
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Does status.TX_MODE = 1? If Yes, Master wants transmit mode – Exit ISR, indicate Master wants Slv-Xmit mode If No, Master wants Slave-Recv mode – dummy = S1DAT, read to release bus – Exit ISR, ready to recv data ...
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SPI (synchronous peripheral interface) 24 SPI (synchronous peripheral interface) uPSD34xx devices support one serial SPI interface in Master Mode only. This is a three- or four-wire synchronous communication channel, capable of full-duplex operation on 8-bit serial data transfers. The four ...
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SPI bus features and communication flow The SPICLK signal is a gated clock generated from the uPSD34xx (Master) and regulates the flow of data bits. The Master may transmit at a variety of baud rates, and the SPICLK ...
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SPI (synchronous peripheral interface) Figure 45. SPI full-duplex data exchange Figure 46. SPI receive operation example SPICLK (SPO=0) SPICLK (SPO=1) SPIRXD RISF RORIS BUSY SPIINTR SPIRDR Full interrupt requested 136/293 Master Device SPI Bus SPIRxD 8-Bit Shift Register SPITxD SPICLK ...
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Figure 47. SPI transmit operation example SPICLK (SPO=0) SPICLK (SPO=1) SPITXD TISF TEISF BUSY SPISEL SPIINTR SPITDR Empty interrupt requested 24.4 SPI SFR registers Six SFR registers control the SPI interface: ● SPICON0 (Table ● SPICON1 (Table ● SPITDR ...
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SPI (synchronous peripheral interface) Figure 48. SPI interface, master mode only INTR to 8032 PERIPH_CLK (f OSC ) 8 24.5 SPI configuration The SPI interface is reset by the MCU reset, and firmware needs to initialize the SFRs SPICON0, SPICON1, ...
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For example, if SPICLKD contains 0x24, SPICLK has the frequency of PERIH_CLK divided by 36 decimal. The SPICLK frequency must be set low enough to allow the MCU time to read ...
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SPI (synchronous peripheral interface) Table 63. SPICON0: control register 0 (SFR D6h, reset value 00h) Bit 7 Bit 6 – TE Bit Symbol 7 – SPIEN 3 SSEL 2 FLSB 1 SPO 0 – 140/293 ...
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Table 64. SPICON1: SPI interface control register 1 (SFR D7h, reset value 00h) Bit 7 Bit 6 – – Bit Symbol 7-4 – 3 TEIE 2 RORIE 1 TIE 0 RIE Table 65. SPICLKD: SPI prescaler (clock divider) register ...
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SPI (synchronous peripheral interface) Table 66. SPISTAT: SPI interface status register (SFR D3h, reset value 02h) Bit 7 Bit 6 – – Bit Symbol 7-5 – 4 BUSY 3 TEISF 2 RORISF 1 TISF 0 RISF 142/293 Bit 5 Bit ...
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USB interface uPSD34xx devices provide a full speed USB (Universal Serial Bus) device interface. The serial interface engine (SIE) provides the interface between the CPU and the USB (see Figure 49). Note: 1 For a list of known ...
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USB interface Figure 49. USB module block diagram D– USB– Transceiver D+ USB+ 25.1 Basic USB concepts The Universal Serial Bus (USB) is more complex than the standard serial port and requires familiarity with the specification to fully understand how ...
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Endpoints Each USB device contains a collection of independent endpoints, with an endpoint being the destination of a communication flow between client software and the device. By design, each USB device’s endpoints are given specific unique identifiers called ...
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USB interface The data packet contains a DATA1 or DATA0 PID USB system, the host or device that is sending data is responsible for toggling the data PID between DATA0 and DATA1. The receiving device keeps track of ...
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Types of transfers The USB specification defines four types of transfers, Bulk, Interrupt, Isochronous, and Control. Note: The uPSD34xx supports all types of transfers except Isochronous. ● Bulk Transfers (see Bulk data is transferred in both directions and ...
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USB interface ● Control Transfers (see Control transfers are used to configure and send commands to a device. Control transfers consist of two or three stages: – SETUP This stage always consists of a data packet with eight bytes of ...
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Figure 53. Control transfer SETUP ADDR Token Packet IN ADDR Token Packet OUT ADDR Token Packet 25.3 Endpoint FIFOs The uPSD34xx’s USB module includes 5 endpoints and 10 FIFOs. Each endpoint has two FIFOs with one for IN and ...
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USB interface Table 68. uPSD34xx supported endpoints Endpoint 0 Control 0 Control 1 Bulk/Interrupt OUT 1 Bulk/Interrupt IN 2 Bulk/Interrupt OUT 2 Bulk/Interrupt IN 3 Bulk/Interrupt OUT 3 Bulk/Interrupt IN 4 Bulk/Interrupt OUT 4 Bulk/Interrupt In 25.3.3 FIFO pairing The ...
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Figure 54. FIFOs with no Pairing Serial Interface Engine ● Pairing FIFOs Example Now assume that IN Endpoint1 and Endpoint2 FIFOs are paired for double buffering and the same 1024 bytes of data are to be transferred to the ...
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USB interface Figure 55. FIFO pairing example (1/2 IN paired and 3/4 OUT paired) Serial Interface Engine 25.3.4 Reading and writing FIFOs There are a total of ten 64-byte FIFOs. Each of the five Endpoints has two FIFOs, one IN ...
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Command Value register (USCV). The USB Setup Command Index register (USCI) is used to select the byte from the command buffer that is read when accessing the USCV register. 25.4 USB registers The USB module is controlled via registers ...
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USB interface SFR SFR Addr Name 7 (hex) EB UIF3 – EC UCTL – ED USTA – USEL DIR F1 UCON – F2 USIZE – F3 UBASEH BASEADDR F4 UBASEL F5 USCI – F6 USCV Note: Bits marked ...
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Table 70. USB device address register (UADDR 0E2h, reset value 00h) Bit 7 Bit 6 – Bit Symbol 7 – 6:0 USBADDR Table 71. Pairing control register (UPAIR 0E3h, reset value 00h) Bit 7 Bit 6 – – Bit ...
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USB interface The USB interrupt priority can be set to low or high. For the best USB response time and to maximize data transfer times, the USB interrupt should be set to the highest priority (see the Section 13: Interrupt ...
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USB IN FIFO Interrupt Enable Register (UIE1) When an endpoint’s IN FIFO has been successfully sent to the host with an IN transaction, the FIFO becomes empty. The UIE1 register is used to enable each endpoint’s IN FIFO ...
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USB interface ● USB IN FIFO NAK Interrupt Enable Register (UIE3) When an endpoint’s IN FIFO is empty and an IN transaction to that endpoint has been received, the SIE sends a NAK handshake token since there is no data ...
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USB Global Interrupt Flag Register (UIF0) There are many different events that generate a USB interrupt requiring a number of registers to indicate the cause of the interrupt. To more efficiently identify the cause of the interrupt, the ...
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USB interface ● USB IN FIFO Interrupt Flag (UIF1) The USB IN FIFO Interrupt Flag register (see when an IN Endpoint FIFO that was full becomes empty. Once set, firmware must clear the flag by writing a '0' to the ...
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USB OUT FIFO Interrupt Flag (UIF2) The USB OUT FIFO Interrupt Flag register (see when an OUT Endpoint FIFO that was empty becomes full. Once set, firmware must clear the flag by writing a '0' to the appropriate ...
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USB interface ● USB IN FIFO NAK Interrupt Flag (UIF3) The USB IN FIFO NAK Interrupt Flag register (see indicate when an IN Endpoint FIFO is not ready. The Endpoint FIFO is not ready when data has not been loaded ...
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USB Control Register (UCTL) The USB Control Register (see FIFOs visible in the XDATA space and for generating a remote wakeup signal. Upon a reset, the USB module is disabled and must be enabled by the CPU for ...
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USB interface ● USB Endpoint0 Status (USTA) The USB Endpoint0 Status register (see occur on the USB that are directed to endpoint0. Table 81. USB endpoint0 status (USTA 0EDh, reset value 00h) Bit 7 Bit 6 – – Bit Symbol ...
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USB Endpoint Select Register (USEL) Endpoints share the same XDATA space for FIFOs as well as the same SFR addresses for Control and FIFO Valid Size registers. The USB Endpoint Select Register (see Table 82) is used to ...
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USB interface ● USB Endpoint Control Register (UCON) The Endpoint selected by the USB Endpoint Select Register (see page 165) determines the direction and FIFO (IN or OUT) that is controlled by the USB Endpoint Control Register (see to control ...
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Bit Symbol 0 BSY ● USB FIFO Valid Size (USIZE) The Endpoint selected by the USB Endpoint Select Register (see page 165) determines the direction and FIFO that is controlled by the USB FIFO Valid Size (see Table loaded ...
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USB interface ● USB FIFO Base Address High and Low Registers (UBASEH and UBASEL) All 10 Endpoint FIFOs share the same 64-byte address range. The 16-bit base address for the FIFOs is specified using the USB Base Address registers (see ...
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USB Setup Command Index and Value Registers (USCI and USCV) When a Setup/Data packet is received over the USB, the 8 bytes of data received are stored in a command buffer. The USB Setup Command Index Register (see ...
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USB interface 25.5 Typical connection to USB Connecting the uPSD34xx to the USB is simple and straightforward. typical self-powered example requiring only three resistors and a USB power detection circuit. The USB power detection circuit detects when the device has ...
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Analog-to-digital convertor (ADC) The ADC unit in the uPSD34xx is a SAR type ADC with an SAR register, an auto-zero comparator and three internal DACs. The unit has 8 input channels with 10-bit resolution. The A/D converter has ...
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Analog-to-digital convertor (ADC) Figure 57. 10-bit ADC AV REF AV REF P1.0 ADC0 P1.1 ADC1 P1.2 ADC2 P1.3 ADC3 P1.4 ADC4 P1.5 ADC5 P1.6 ADC6 P1.7 ADC7 172/293 ANALOG MUX CONTROL SELECT ADAT1 ACON REG uPSD34xx 10-BIT SAR ADC ADC ...
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Table 89. ACON register (SFR 97h, reset value 00h) Bit 7 Bit 6 AINTF AINTEN Bit Symbol 7 AINTF 6 AINTEN 5 ADEN 4.. 2 ADS2 ADST 0 ADSF Bit 5 Bit 4 Bit 3 ADEN ADS2 ...
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Analog-to-digital convertor (ADC) Table 90. ADCPS register details (SFR 94h, Reset Value 00h) Bit Symbol 7:4 – 3 ADCCE 2:0 ADCPS[2:0] Table 91. ADAT0 register (SFR 95h, reset value 00h) Bit Symbol 7:0 – Table 92. ADAT1 register (SFR 96h, ...
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Programmable counter array (PCA) with PWM There are two Programmable Counter Array blocks (PCA0 and PCA1) in the uPSD34xx. A PCA block consists of a 16-bit up-counter, which is shared by three TCM (Timer Counter Module). A TCM ...
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Programmable counter array (PCA) with PWM Table 93. PCA0 and PCA1 Registers SFR Address PCA0 PCA1 A9, BD, AA, BE ...
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Table 94. CCON2 register bit definition (SFR 0FBh, reset value 10h) Bit 7 Bit 6 – – Bit Symbol 4 PCA0CE PCA0PS 3:0 [3:0] Table 95. CCON3 register bit definition (SFR 0FCh, reset value 10h) Bit 7 Bit 6 ...
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Programmable counter array (PCA) with PWM 27.6 Toggle mode In this mode, the user writes a value to the TCM's CAPCOM registers and enables the comparator. When there is a match with the Counter output, the output of the TCM ...
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Figure 60. PWM mode - (x8), fixed frequency OVERFLOW Note 27.8 PWM mode - (x8), programmable frequency In this mode, the ...
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Programmable counter array (PCA) with PWM Figure 61. PWM mode - (x8) programmable frequency PWM FREQ COMPARE PWMFm PWMFm = PCACLm PCACHm ENABLE 8-bit COMPARATORm Note ...
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PWM mode - fixed frequency, 10-bit The 10-bit PWM logic requires that all 3 TCMs in PCA0 or PCA1 operate in the same 10-bit PWM mode. The 10-bit PWM operates in a similar manner as the 16-bit PWM, ...
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Programmable counter array (PCA) with PWM Table 96. PCA0 control register PCACON0 (SFR 0A4h, reset value 00h) Bit 7 Bit 6 EN-ALL EN_PCA Bit Symbol 7 EN-ALL 6 EN_PCA 5 EOVFI 4 PCAIDLE 3 – 2 10B_PWM CLK_SEL 1-0 [1:0] ...
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Table 98. PCA status register PCASTA (SFR 0A5h, reset value 00h) Bit 7 Bit 6 OVF1 INTF5 Bit Symbol 7 OFV1 6 INTF5 5 INTF4 4 INTF3 3 OVF0 2 INTF2 1 INTF1 0 INTF0 27.13 TCM interrupts There ...
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Programmable counter array (PCA) with PWM Table 99. TCMMODE0 - TCMMODE5 (6 registers, reset value 00h) Bit 7 Bit 6 EINTF E_COMP Bit Symbol 7 EINTF 6 E_COMP 1 - Enable the comparator when set 5 CAP_PE 4 CAP_NE 3 ...
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PSD module The PSD Module is stacked with the MCU Module to form the uPSD34xx, see Hardware description on page two separate modules interface with each other at the 8032 Address, Data, and Control interface blocks in Figure ...
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PSD module 28.1.1 8032 address/data/control interface These signals attach directly to the MCU Module to implement a 16-bit multiplexed 8051- style bus between the two stacked die. The MCU instruction prefetch and branch cache logic resides on the MCU Module, ...
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PSEN) or XDATA space (accessed with RD or WR) as defined with PSDsoft Express. The user only has to specify an address range for each segment, and specify if Secondary Flash memory will reside ...
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PSD module signals used to “page” memory beyond the 64K byte limit (program space or XDATA). Most 8051 compilers directly support memory paging, also known as memory banking. If memory paging is not needed not all eight page ...
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There are 69 GPLD inputs which include: 8032 address and control signals, Page Register outputs, PSD Module Port pin inputs, and ...
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... Port C, TSTAT and TERR, in addition to TMS, TCK, TDI and TDO, and this is referred to as “6-pin JTAG”. The FlashLINK JTAG programming cable is available from STMicroelectronics and PSDsoft Express software is available at no charge from www.st.com/psm. More JTAG ISP information maybe found in JTAG debug on page The MCU module is also included in the JTAG chain within the uPSD34xx device for 8032 debugging and emulation ...
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Power management The PSD Module has bits in csiop registers that are configured at run-time by the 8032 to reduce power consumption of the GPLD. The Turbo Bit in the PMMR0 Register can be set to logic ’1’ ...
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PSD module 28.2.1 8032 program address space In the example of three memory pages in the upper half of program address space, and the remaining two sectors of Main Flash memory (fs0, fs1) reside in the lower half of program ...
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Table 103. HDL statement example generated from PSDsoft express for memory map = ((address ≥ ^h0000) & (address ≤ ^h1FFF)); rs0 = ((address ≥ ^h2000) & (address ≤ ^h20FF)); csiop = ((address ≥ ^h0000) & (address ≤ ^h3FFF)); fs0 ...
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PSD module maintained by alternating between the two flash sectors. For example, a data set of 128 bytes is written and maintained by software in a distributed fashion across one 8K byte sector of Secondary Flash memory until it becomes ...
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Figure 67. Mapping: all Flash in code space ● Figure 68 Place the larger Main Flash Memory into XDATA space and the smaller Secondary Flash into program space for systems that need a large amount of Flash for data ...
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PSD module from the Secondary Flash memory in program space. After the writing is complete, the Main Flash can be “reclassified” back to program space, then execution can continue from the new code in Main Flash memory. The mapping example ...
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The VM register One of the csiop registers (the VM Register) controls whether or not the 8032 bus control signals RD, WR, and PSEN are routed to the Main Flash memory, or the Secondary Flash memory. Routing of ...
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PSD module Figure 70. VM register control of memories 8032 Address 53 Other PLD Inputs WR VM REG BIT 4 VM REG BIT REG BIT 2 VM REG BIT 1 PSEN Figure 71. VM register example corresponding ...
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The Flash memories are 16-bit wide when Program Memory space and are 8-bit wide when the Data Space. When the Flash memory is configured in both “Program Space” and “Data Space,” the Flash ...
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PSD module Port A Register Name (80-pin) Drive Select 08h Input 0Ah Macrocells Enable Out OCh Output Macrocells AB (MCELLAB) Output Macrocells BC (MCELLBC) Mask Macrocells AB Mask Macrocells BC Main Flash Sector Protection Security Bit and Secondary Flash Sector ...