UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 15

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

uPSD34xx
Table 2.
RESET_IN
JTAGTMS
JTAGTCK
Port Pin
DEBUG
XTAL1
XTAL2
PSEN
PC2
PC3
PC4
ALE
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Pin definitions
Signal
TSTAT
Name
V
TERR
TMS
TCK
STBY
80-Pin
No.
63
68
48
49
35
34
32
28
26
24
22
21
80
78
76
74
73
71
67
66
20
17
16
15
4
8
9
52-Pin
No.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
44
31
32
52
51
50
49
48
46
43
42
13
12
11
5
(1)
In/Out
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
PSEN Signal,
external bus
Address Latch
signal, external bus
Active low reset
input
Oscillator input pin
for system clock
Oscillator output pin
for system clock
I/O to the MCU
Debug Unit
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
JTAG pin (TMS)
JTAG pin (TCK)
General I/O port pin
General I/O port pin
General I/O port pin
Basic
SRAM Standby
Status (TSTAT)
Status (TERR)
Optional JTAG
Optional JTAG
voltage input
Alternate 1
Function
(V
STBY
)
All Port A pins
support:
1.
2.
3.
4.
All Port B pins
support:
1.
2.
3.
output, or PLD input
output, or PLD input
output, or PLD input
Pin descriptions
PLD, Macrocell
PLD, Macrocell
PLD Macrocell
Alternate 2
PLD Macro-
cell outputs, or
PLD inputs, or
Latched
Address Out
(A0-A7), or
Peripheral I/O
Mode
PLD Macro-
cell outputs, or
PLD inputs, or
Latched
Address Out
(A0-A7 or
A8-A15)
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