UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet
UPSD3433E-40U6
Specifications of UPSD3433E-40U6
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UPSD3433E-40U6 Summary of contents
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... PWM operation – 12 Interrupt sources with two external interrupt pins ■ Packages ® – ECOPACK compliant Table 1. Device summary Reference uPSD3422 UPSD3422E, UPSD3422EV uPSD3433E UPSD3433E, UPSD3433EV uPSD3434 UPSD3434E, UPSD3434EV uPSD3454 UPSD3454E, UPSD3454EV Rev 5 LQFP80 (U), 80-lead, thin, quad, flat Part number 1/300 www.st.com 1 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 7.7.3 7.7.4 7.7.5 7.7.6 8 Special function registers (SFR ...
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Contents 13.1.6 13.1.7 13.1.8 13.1.9 14 MCU clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 19.4 JTAG debug reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 22.2 Pulse width selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 25.1.4 25.2 Types of transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 28.1 PSD module functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 28.1.1 28.1.2 28.1.3 28.1.4 28.1.5 ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 28.5.8 28.5.9 28.5.10 Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 28.5.45 Drive select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 33 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 49. BUSCON: bus control register (SFR 9Dh, reset value EBh Table ...
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List of tables Table 98. UPSD34xx supported endpoints ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 150. PCA1 control register PCACON1 (SFR 0BCh, reset value 00h 188 Table 151. PCA1 register bit ...
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List of tables Table 202. Power management mode register PMMR3 (address = csiop + offset C7h 250 Table 203. Function status during power-up reset, warm reset, power-down mode . . ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 49. USB packets in a USB transfer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 101. Synchronous Clock mode timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The Turbo Plus UPSD34xx Series combines a powerful 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal embedded controller. At its core is a fast 4-cycle 8032 MCU ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 1. Block diagram P3.0:7 P1.0:7 P4.0:7 USB+, USB– uPSD34xx (3) 16-bit Timer/ Turbo PFQ Counters 8032 & (2) Core BC External Interrupts UART0 (8) GPIO, Port 3 (8) GPIO, Port 1 (8) ...
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Pin descriptions 2 Pin descriptions Figure 2. LQFP52 connections PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3 USB GND 9 USB– 10 PC2 11 JTAG TCK ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 3. LQFP80 connections PD2/CSI P3.3/TG1/EXINT1 PD1/CLKIN ALE PC7 JTAG TDO JTAG TDI DEBUG PC4/TERR 3 (1) USB+ ( GND USB– PC3/TSTAT PC2 JTAG TCK (2) SPISEL /PCACLK1/P4.7 (2) SPITXD /TCM5/P4.6 ...
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Pin descriptions Table 2. Pin definitions Signal 80-pin Port pin name No. MCUAD0 AD0 36 MCUAD1 AD1 37 MCUAD2 AD2 38 MCUAD3 AD3 39 MCUAD4 AD4 41 MCUAD5 AD5 43 MCUAD6 AD6 45 MCUAD7 AD7 47 P1.0 T2 ADC0 52 ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 2. Pin definitions (continued) Signal 80-pin Port pin name No. P3.1 TXD0 77 EXINT0 P3.2 79 TGO P3.3 INT1 P3.6 SDA 44 P3.7 SCL 46 T2 P4.0 33 ...
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Pin descriptions Table 2. Pin definitions (continued) Signal 80-pin Port pin name No. ALE 4 RESET_IN 68 XTAL1 48 XTAL2 49 DEBUG 8 PA0 35 PA1 34 PA2 32 PA3 28 PA4 26 PA5 24 PA6 22 PA7 21 PB0 ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 2. Pin definitions (continued) Signal 80-pin Port pin name No. PC7 5 PD1 CLKIN 3 PD2 CSI 1 USB+ 11 USB– 14 3 ...
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Hardware description 3 Hardware description The UPSD34xx has a modular architecture built from a stacked die process. There are two dice, one is designated “MCU module” in this document, and the other is designated “PSD module” (see Figure 4 on ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 4. Functional modules Port 3 - UART0, Intr, Timers Port Clock Unit Dual UARTs Interrupt Dedicated Memory Interface Prefetch, Branch Cache 8-Bit/16-Bit Die-to-Die Bus Enhanced MCU Interface PSD Page Register Decode PLD ...
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Memory organization 4 Memory organization The 8032 MCU core views memory on the MCU module as “internal” memory and it views memory on the PSD module as “external” memory, see Internal memory on the MCU module consists of DATA, IDATA, ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 4.1 Internal memory (MCU module, standard 8032 memory: DATA, IDATA, SFR) 4.1.1 DATA memory The first 128 bytes of internal SRAM ranging from address 0000h to 007Fh are called DATA, which can be accessed using 8032 ...
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Memory organization 4.2.1 Program memory External program memory is addressed by the 8032 using its 16-bit program counter (PC) and is accessed with the 8032 signal, PSEN. Program memory can be present at any address in program space between 0000h ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 5 8032 MCU core performance enhancements Before describing performance features of the UPSD34xx, let us first look at standard 8032 architecture. The clock source for the 8032 MCU creates a basic unit of timing called a ...
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MCU core performance enhancements Figure 7. Instruction pre-fetch queue and branch cache Branch Cache (BC) Instruction byte 16-bit program memory Instruction byte on PSD module 5.1 Pre-fetch queue (PFQ) and branch cache (BC) The PFQ is always working to ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 four MCU clocks). But it is also important to understand PFQ operation on multi-cycle instructions. 5.2 PFQ example, multi-cycle instructions Let us look at a string of two-byte, two-cycle instructions in three instructions executed sequentially in ...
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MCU core performance enhancements Figure 9. UPSD34xx multi-cycle instructions compared to standard 8032 A1 A2 uPSD34xx Std 8032 Byte 1 36/300 UPSD3422, UPSD3433, UPSD3434, UPSD3454 Three 2-byte, 2-cycle Instructions, uPSD34xx vs. Standard 8032 24 Clocks Total (4 clocks per ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 6 MCU module description This following sections provide a detailed description of the MCU module system functions and peripherals, including: ● 8032 MCU registers ● Special function registers ● 8032 addressing modes ● UPSD34xx instruction set ...
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MCU registers 7 8032 MCU registers The UPSD34xx has the following 8032 MCU core registers, also shown in Figure 10. 8032 MCU registers 7.1 Stack pointer (SP) The 8-bit register which holds the current location of ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 7.4 Accumulator (ACC) This is an 8-bit general purpose register which holds a source operand and receives the result of arithmetic operations. The ACC register can also be the source or destination of logic and data ...
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MCU registers 7.7.5 Overflow flag (OV) The OV flag is set when: an ADD, ADDC, or SUBB instruction causes a sign change; a MUL instruction results in an overflow (result greater than 255); a DIV instruction causes a divide- ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 8 Special function registers (SFR) A group of registers designated as special function register (SFR) is shown in page 42. SFRs control the operating modes of the MCU core and also control the peripheral interfaces and ...
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Special function registers (SFR) CAPCOML4, CAPCOMH4, TCMMODE4, CAPCOML5, CAPCOMH5, TCMMODE5, PWMF0, PMWF1 ● SPI interface registers SPICLKD, SPISTAT, SPITDR, SPIRDR, SPICON0, SPICON1 2 ● interface registers S1SETUP, S1CON, S1STA, S1DAT, S1ADR ● Analog to digital converter registers ACON, ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 5. SFR memory map with direct address and reset value (continued) SFR SFR addr name 7 6 (hex) 94 ADCPS – – 95 ADAT0 96 ADAT1 – – 97 ACON AINTF AINTEN SM0 SM1 (1) ...
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Special function registers (SFR) Table 5. SFR memory map with direct address and reset value (continued) SFR SFR addr name 7 6 (hex) P3.7 P3.6 ( <B7h> <B6h> CAPCOM B1 H1 CAPCOM B2 L2 CAPCOM ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 5. SFR memory map with direct address and reset value (continued) SFR SFR addr name 7 6 (hex) CAPCOM C1 L3 CAPCOM C2 H3 CAPCOM C3 L4 CAPCOM C4 H4 CAPCOM C5 L5 CAPCOM C6 ...
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Special function registers (SFR) Table 5. SFR memory map with direct address and reset value (continued) SFR SFR addr name 7 6 (hex) DD S1STA GC STOP DE S1DAT DF S1ADR ( <bit addresses: E7h, E6h, E5h, E4h, ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 5. SFR memory map with direct address and reset value (continued) SFR SFR addr name 7 6 (hex) F9 CCON0 PLLM[4] PLLEN FA CCON1 FB CCON2 – – FC CCON3 – – ...
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The 8032 MCU uses 11 different addressing modes listed below: ● Register ● Direct ● Register indirect ● Immediate ● External direct ● External indirect ● Indexed ● Relative ● Absolute ● Long ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 9.4 Immediate addressing This mode uses 8-bits of data (a constant) contained in the second byte of the instruction, and stores it into the memory location or register indicated by the first byte of the instruction. ...
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Indexed addressing This mode is used for the MOVC instruction which allows the 8032 to read a constant from program memory (not data memory). MOVC is often used to read look-up tables that are embedded in ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 9.11 Bit addressing This mode allows setting or clearing an individual bit without disturbing the other bits within an 8-bit value of internal SRAM. Bit Addressing is only available for certain locations in 8032 DATA and ...
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UPSD34xx instruction set summary 10 UPSD34xx instruction set summary Tables 6 through number of bytes and number of machine cycles required to implement each instruction. This is the standard 8051 instruction set. The meaning of “machine cycles” is how many ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 6. Arithmetic instruction set (continued) (1) Mnemonic and use DEC @Ri INC DPTR MUL AB DIV All mnemonics copyrighted ©Intel Corporation 1980. Table 7. Logical instruction set (1) Mnemonic and use ...
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UPSD34xx instruction set summary Table 8. Data transfer instruction set (1) Mnemonic and use MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 9. Boolean variable manipulation instruction set (1) Mnemonic and use CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV ...
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UPSD34xx instruction set summary Table 10. Program branching instruction set (continued) (1) Mnemonic and use @Ri, #data, CJNE rel DJNZ Rn, rel DJNZ direct, rel 1. All mnemonics copyrighted ©Intel Corporation 1980. Table 11. Miscellaneous instruction set (1) Mnemonic and ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 11 Dual data pointers XDATA is accessed by the External Direct addressing mode, which uses a 16-bit address stored in the DPTR register. Traditional 8032 architecture has only one DPTR register. This is a burden when ...
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Dual data pointers 11.2 Data pointer mode register, DPTM (86h) The two “background” data pointers, DPTR0 and DPTR1, can be configured to automatically increment, decrement, or stay the same after a MOVX instruction accesses the DPTR register. Only the currently ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 8051 assembly code example MOV MOV MOV MOV MOV MOV LOOP: MOVX MOVX (1) DJNZ MOV MOV Note: 1 The code loop where the data transfer takes place is only 3 lines of code. R7, #COUNT ...
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Debug unit 12 Debug unit The 8032 MCU module supports run-time debugging through the JTAG interface. This same JTAG interface is also used for In-System Programming (ISP) and the physical connections are described in the PSD module section, page 257. ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 module on page – The duration of a pulse, generated when the Event pin configured as an output, is one MCU clock cycle. This is an active-low signal, so the first edge ...
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Interrupt system 13 Interrupt system The UPSD34xx has an 12-source, two priority level interrupt structure summarized in Table 17. Firmware may assign each interrupt source either high or low priority by writing to bits in the SFRs named, IP and ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 If an interrupt flag is not cleared after servicing the interrupt, an unwanted interrupt will occur upon exiting the ISR. After the interrupt is serviced, the last instruction executed by the ISR is RETI. The RETI ...
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Interrupt system Figure 12. Enabling and polling interrupts Interrupt Sources Reserved 13.1 Individual interrupt sources 13.1.1 External interrupts Int0 and Int1 External interrupt inputs on pins EXTINT0 and EXTINT1 (pins 3.2 and 3.3) are either edge- triggered or level-triggered, depending ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 13.1.2 Timer 0 and 1 overflow interrupt Timer 0 and Timer 1 interrupts are generated by the flag bits TF0 and TF1 when there is an overflow condition in the respective Timer/Counter register (except for Timer ...
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Interrupt system 13.1.9 USB interrupt The USB interrupt has multiple sources. The ISR must read the USB interrupt flag registers (UIF0-3) to determine the source of the interrupt. The USB interrupt can be activated by any of the following four ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 21. IEA register bit definition (continued) Bit Symbol 3 – 2 – ( EUSB Enable Interrupt Disable Interrupt. Table 22. IP: interrupt priority register (SFR B8h, reset ...
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MCU clock generation 14 MCU clock generation Internal system clocks generated by the clock generation unit are derived from the signal, XTAL1, shown in external crystal or oscillator device. The SFR named CCON0 the clock generation unit. There are two ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 14.2.2 USB_CLK The UPSD34xx has a dedicated analog phase locked loop (PLL) that can be configured to generate the 48MHz USB_CLK clock on a wide range of f must be at 48MHz for the USB to ...
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MCU clock generation Figure 13. Clock generation logic PCON[1]: PD, Power-Down Mode XTAL1 (f OSC ) PCON[1] CCON0[6] Table 27. CCON0: clock control register (SFR F9h, reset value 50h) Bit 7 Bit 6 PLLM[4] PLLEN Table 28. CCON0 register bit ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 28. CCON0 register bit definition (continued) Bit Symbol 3 CPUAR 2:0 CPUPS Table 29. CCON1 PLL control register (SFR FAh, reset value 00h) Bit 7 Bit 6 Table 30. CCON1 register bit definition Bit Symbol ...
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Power saving modes 15 Power saving modes The UPSD34xx is a combination of two die, or modules, each module having its own current consumption characteristics. This section describes reduced power modes for the MCU module. See Section 28.1.16: Power management ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 15.2 Power-down mode Power-down mode will halt the 8032 core and all MCU peripherals (Power-down mode blocks MCU_CLK, USB_CLK, and PERIPH_CLK). This is the lowest power state for the MCU module. When the PSD module is ...
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Power saving modes Table 31. MCU module port and peripheral status during reduced power modes Mode Ports Maintain Idle data Power- Maintain down data 1. The Watchdog Timer is not active during Idle mode. Other supervisor functions ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 34. PCON register bit definition (continued) Bit Symbol IDL R/W Activate Power-down mode R Not in Power-down mode 1 = Enter Power-down mode Activate Idle mode R Not ...
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Oscillator and external components 16 Oscillator and external components The oscillator circuit of UPSD34xx devices is a single stage, inverting amplifier in a Pierce oscillator configuration. The internal circuitry between pins XTAL1 and XTAL2 is basically an inverter biased to ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 14. Oscillator and clock connections XTAL1 (in) C1 Ceramic resonator Crystal, fundamental mode (3-40MHz) Crystal, overtone mode (25-40MHz) XTAL2 (out) XTAL C2 (f OSC ) XTAL (f OSC ) ...
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I/O ports of mcu module 17 I/O ports of mcu module The MCU module has three 8-bit I/O ports: Port 1, Port 3, and Port 4. The PSD module has four other I/O ports: Port and D. ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 17.1.1 GPIO function Ports in GPIO mode operate as quasi-bidirectional pins, consistent with standard 8051 architecture. GPIO pins are individually controlled by three SFRs: ● SFR, P1 (Table 35 on page ● SFR, P3 (Table 37 ...
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I/O ports of mcu module CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All other types of reads to port SFRs will read the actual pin logic level and not the port latch. This is consistent with 8051 architecture. Figure ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 17. MCU I/O cell block diagram for port 3 Enable_I Select_Alternate_Func Digital_Alt_Func_Data_Out P3.X SFR Read Latch (for R-M-W instructions) MCU_Reset 8032 Data Bus Bit GPIO P3.X SFR Write Latch P3.X SFR Read Pin Digital_Pin_Data_In Figure ...
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I/O ports of mcu module Table 36. P1 register bit definition (continued) Bit Symbol 2 P1.2 1 P1.1 0 P1.0 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 17.1.4 Alternate functions There are five SFRs used to control the mapping of alternate functions onto MCU port pins, and these SFRs are depicted as switches in ● Port 3 uses the SFR, P3SFS ● Port ...
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I/O ports of mcu module Table 41. P3SFS: Port 3 special function select register (SFR 91h, reset value 00h) Bit 7 Bit 6 P3SFS7 P3SFS6 Table 42. P3SFS register bit definition Port 3 Pin R/W 0 R,W 1 R,W 2 ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 45. P1SFS0 and P1SFS1 details (continued) Port 1 Pin R/W 6 R,W 7 R,W Table 46. P4SFS0: Port 4 special function select 0 register (SFR 92h, reset value 00h) Bit 7 Bit 6 P4SF07 P4SF06 ...
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MCU bus interface 18 MCU bus interface The MCU module has a programmable bus interface which is a modified 8032 bus with 16 multiplexed address and data lines. The bus supports four types of data transfer (16 bit), ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 A[10:8] and the remaining pins can be configured for other functions such as generating chip selects to the external devices. Figure 19. Connecting external devices using ports A and B for address AD[15:0] MCU Module AI10434 ...
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MCU bus interface It is not possible to specify in the BUSCON register a different number of MCU_CLK periods for various address ranges. For example, the user cannot specify 4 MCU_CLK periods for RD read cycles to one address range ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 50. BUSCON register bit definition Bit Symbol 7 EPFQ 6 EBC 5:4 WRW[1:0] 3:2 RDW[1:0] 1:0 CW[1:0] R/W Enable pre-fetch queue R PFQ is disabled 1 = PFQ is enabled (default) Enable branch ...
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MCU bus interface Table 51. Number of MCU_CLK periods required to optimize bus transfer rate MCU clock frequency, MCU_CLK (f 40 MHz, Turbo mode PSD 40 MHz, Non-turbo mode PSD 36 MHz, Turbo mode PSD 36 MHz, Non-turbo mode PSD ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 19 Supervisory functions Supervisory circuitry on the MCU module will issue an internal reset signal to the MCU module and simultaneously to the PSD module as a result of any of the following four events: ● ...
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Supervisory functions 19.2 Low V voltage detect, LVD CC An internal reset is generated by the LVD circuit when After V LV_THRESH asserted for t RST_ACTV disabled by SFR), even in Idle mode and Power-down mode. The ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 To prevent the WDT from timing out and generating a reset, firmware must repeatedly write some value to WDRST before the count reaches FFFFFh. Whenever WDRST is written, the upper 8 bits of the 24-bit counter ...
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Supervisory functions In this example 100ns (4 MCU_CLK periods x 25ns) MACH_CYC N OVERFLOW WDT PERIOD The actual value will be slightly longer due to PFQ/BC. 19.5.1 Firmware example The following 8051 assembly code illustrates how to operate ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 55. WDRST register bit definition Bit Symbol [7:0] WDRST R/W This SFR is the upper byte of the 24-bit WDT up-counter. Writing this SFR sets the upper byte of the counter to the written value, ...
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Standard 8032 timer/counters 20 Standard 8032 timer/counters There are three 8032-style 16-bit Timer/Counter registers (Timer 0, Timer 1, Timer 2) that can be configured to operate as timers or event counters. There are two additional 16-bit Timer/Counters in the Programmable ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 period ( OSC, sample period must be calculated based on the resultant, longer, MCU_CLK frequency. In this case, an external clock signal on pins C0, C1 should have a duration longer than ...
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Standard 8032 timer/counters 20.4 SFR, TMOD Timer 0 and Timer 1 have four modes of operation controlled by the SFR named TMOD (Table 58). 20.5 Timer 0 and Timer 1 operating modes The “Timer” or “Counter” function is selected by ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator fact, in any application not ...
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Standard 8032 timer/counters Figure 24. Timer/counter mode 0: 13-bit counter f OSC C1 pin Gate EXTINT1 pin Figure 25. Timer/counter mode 2: 8-bit Auto-reload f OSC C1 pin Gate EXTINT1 pin Figure 26. Timer/counter mode 3: two 8-bit counters f ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 20.6.1 Capture mode In Capture mode there are two options which are selected by the bit EXEN2 in T2CON. Figure 27 on page 105 If EXEN2 = 0, then Timer 16-bit timer if ...
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Standard 8032 timer/counters Table 61. T2CON register bit definition (continued) Bit Symbol 4 TCLK 3 EXEN2 2 TR2 1 C/T2 0 CP/RL2 Note: 1 The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 62. Timer/counter 2 operating modes (continued) Bits in T2CON SFR RCLK Mode or TCLK 1 Baud rate generator 1 Off x ↓ falling edge. 20.6.3 Baud rate generator mode The RCLK and/or TCLK ...
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Standard 8032 timer/counters in use as a baud rate generator, the pin T2X can be used as an extra external interrupt, if desired. When Timer 2 is running (TR2 = “timer” function in the Baud rate generator ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 63. Commonly used baud rates generated from timer2 (T2CON = 34h) (continued) f MHz OSC baud rate 3.6864 3.6864 3.6864 3.6864 3.6864 1.8432 1.8432 Figure 27. Timer 2 in capture mode f ÷ 12 OSC ...
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Standard 8032 timer/counters Figure 28. Timer 2 in auto-reload mode f ÷ 12 OSC T2 pin Transition Detector T2X pin Figure 29. Timer 2 in baud rate generator mode Note: Oscillator frequency is divided by 2, not 12 like in ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 21 Serial UART interfaces UPSD34xx devices provide two standard 8032 UART serial ports. – The first port, UART0, is connected to pins RxD0 (P3.0) and TxD0 (P3.1) – The second port, UART1 is connected to pins ...
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Serial UART interfaces 21.1.3 Mode 2 Mode 2 provides asynchronous, full-duplex communication using a total of 11 bits per data byte. Data is transmitted through TxD and received through RxD with: a Start Bit (logic '0'); eight data bits (LSB ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 21.2 Serial port control registers The SFR SCON0 controls UART0, and SCON1 controls UART1, shown in Table 67. These registers contain not only the mode selection bits, but also the 9th data bit for transmit and ...
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Serial UART interfaces Table 68. SCON1 register bit definition Bit Symbol 7 SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 21.3 UART baud rates The baud rate in Mode 0 is fixed: Mode ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 21.3.1 Using timer 1 to generate baud rates When Timer 1 is used as the baud rate generator (bits RCLK = 0, TCLK = 0), the baud rates in Modes 1 and 3 are determined by ...
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Serial UART interfaces Table 69. Commonly used baud rates generated from timer 1 (continued) UART mode f OSC Modes 3.6864 Modes 3.6864 Modes 1.8432 Modes 1.8432 21.4 More ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 30. UART mode 0, block diagram Write to SBUF f OSC /12 REN R1 Figure 31. UART mode 0, timing diagram Write to SBUF Send Shift RxD (Data Out) TxD (Shift Clock) TI Write to ...
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Serial UART interfaces 21.5 More about UART mode 1 Refer to the block diagram in page 115. Transmission is initiated by any instruction which writes to SBUF. At the end of a write operation to SBUF, a '1' is loaded ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 32. UART mode 1, block diagram Timer1 Timer2 overflow overflow ÷ SMOD 0 1 TCLK 0 1 RCLK Figure 33. UART mode 1, timing diagram Tx Clock Write to SBUF Send Data Shift ...
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Serial UART interfaces 21.6 More about UART modes 2 and 3 For Mode 2, refer to the block diagram in Figure 35 on page and timing diagram in Keep in mind that the baud rate is programmable to either 1/32 ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 34. UART mode 2, block diagram f OSC /32 ÷ SMOD Figure 35. UART mode 2, timing diagram Tx Clock Write to SBUF Send Data Shift TxD TI Stop Bit Generator Rx Clock ...
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Serial UART interfaces Figure 36. UART mode 3, block diagram Timer1 Timer2 Overflow Overflow ÷ SMOD 0 1 TCLK 0 1 RCLK Figure 37. UART mode 3, timing diagram Tx Clock Write to SBUF Send Data Shift TxD ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 22 IrDA interface UPSD34xx devices provide an internal IrDA interface that will allow the connection of the UART1 serial interface directly to an external infrared transceiver device. The IrDA interface does this by automatically shortening the ...
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IrDA interface The UART1 serial channel can operate in one of four different modes as shown in on page 108 in Section 21: Serial UART interfaces on page used for IrDA communication, UART1 must operate in Mode 1 only, to ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 73. Baud rate of UART#1 for IrDA interface BR3 22.2 Pulse width selection The IrDA interface has two ways to modulate the ...
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IrDA interface Table 74. Recommended CDIV[4:0] values to generate SIRClk (default CDIV[4:0] = 0Fh, 15 decimal) f (MHz) OSC 40.00 36.864, or 36.00 24.00 11.059, or 12.00 7.3728 1. When PULSE bit = 0 (fixed data pulse width), this is ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 interface UPSD34xx devices support one serial I channel, having a bidirectional data signal (SDA, pin P3.6) and a clock signal (SCL, pin P3.7) based on open-drain line drivers, requiring external pull-up resistors, ...
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I C interface 23.2 Communication flow data flow control is based on the fact that all I lines with open-drain (or open-collector) line drivers pulled up with external resistors, creating a wired-AND situation. This means that ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 A few things to know related to these transfers: ● Either the Master or Slave device can hold the SCL clock line low to indicate it needs more time to handle a byte transfer. An indefinite ...
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I C interface The interface may operate as either a Master or a Slave within a given application, controlled by firmware writing to SFRs. By default after a reset, the I SCL/P3.7 pins default to GPIO input mode, high ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 23.6 General call address A General Call (GC) occurs when a Master-Transmitter initiates a transfer containing a Slave address of 0000000b, and the R/W bit is logic 0. All Slave devices capable of responding to this ...
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I C interface 2 Figure 42 interface SIOE block diagram SCL / P3.7 SDA / P3.6 AI09626b 128/300 UPSD3422, UPSD3433, UPSD3434, UPSD3454 Open- Arbitration Input drain output generation Open- Serial DATA IN drain Input output Shift Direction ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 2 23 interface control register (S1CON) Table 75. Serial control register S1CON (SFR DCh, reset value 00h) Bit 7 Bit 6 CR2 ENI1 Table 76. S1CON register bit definition Bit Symbol 7 CR2 6 ...
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I C interface Table 77. Selection of the SCL frequency in Master mode based on f CR2 CR1 These values are beyond ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 79. S1STA register bit definition Bit Symbol STOP 5 INTR 4 TX_MODE 3 BBUSY 2 BLOST 1 ACK_RESP 0 SLV 2 23. data shift register (S1DAT) The S1ADR register serial ...
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I C interface While transmitting, bytes are shifted out MSB first, and when receiving, bytes are shifted in MSB first, through the Acknowledge Bit register as shown in 23.10.1 Bus wait condition After the SIOE finishes receiving a byte ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 2 23. Start sample setting (S1SETUP) The S1SETUP register will be sampled before the SIOE validates the Start condition, giving the SIOE the ability to reject noise or illegal transmissions. Because the minimum duration ...
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I C interface Table 86. Number of I condition) Contents of S1SETUP SS_EN bit ... 1 1 ... 1 Table 87. Start condition hold time bus speed Standard Fast High 1. 833KHz ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 88. S1SETUP examples for various I frequencies (continued bus speed, f SCL Recommended S1SETUP value Number of samples Fast Time between samples Total sampled period Recommended S1SETUP value Number of samples High ...
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I C interface Enable individual I2C interrupt and set priority – SFR IEA.I2C = 1 – SFR IPA.I2C = 1 if high priority is desired Set the Device address for Slave mode – SFR S1ADR = XXh, desired address ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Enable I2C SIOE – SFR S1CON.INI1 = 1 Transmit Address and R/W bit = 1 to Slave – Is bus not busy? (SFR S1STA.BBUSY = 0?) <If busy, then test until not busy> – SFR S1DAT[7:0] ...
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I C interface 23.13.1 Interrupt service routine (ISR typical I C interrupt service routine would handle a interrupt for any of the four combinations of Master/Slave and Transmitter/Receiver. In the example routines above, the firmware sets global ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Else If mode is Master-Receiver: Bus Arbitration lost? (status.BLOST=1?) If Yes, Arbitration was lost: – S1DAT = dummy, write to release bus – Exit ISR, SIOE will switch to Slave Recv mode If No, Aribitration was ...
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I C interface Is this the next to last byte to receive from Slave? If this is the next to last byte, do not allow Master to ACK on next interrupt. – S1CON. don’t let Master return ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Does status.TX_MODE = 1? If Yes, Master wants transmit mode – Exit ISR, indicate Master wants Slv-Xmit mode If No, Master wants Slave-Recv mode – dummy = S1DAT, read to release bus – Exit ISR, ready ...
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SPI (synchronous peripheral interface) 24 SPI (synchronous peripheral interface) UPSD34xx devices support one serial SPI interface in Master Mode only. This is a three- or four-wire synchronous communication channel, capable of full-duplex operation on 8-bit serial data transfers. The four ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 24.1 SPI bus features and communication flow The SPICLK signal is a gated clock generated from the UPSD34xx (Master) and regulates the flow of data bits. The Master may transmit at a variety of baud rates, ...
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SPI (synchronous peripheral interface) Figure 44. SPI full-duplex data exchange Figure 45. SPI receive operation example SPICLK (SPO=0) SPICLK (SPO=1) SPIRXD RISF RORIS BUSY SPIINTR SPIRDR Full interrupt requested 144/300 UPSD3422, UPSD3433, UPSD3434, UPSD3454 Master device SPI bus SPIRxD 8-bit ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 46. SPI transmit operation example SPICLK (SPO=0) SPICLK (SPO=1) SPITXD TISF TEISF BUSY SPISEL SPIINTR SPITDR Empty interrupt requested 24.4 SPI SFR registers Six SFR registers control the SPI interface: ● SPICON0 (Table ● SPICON1 ...
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SPI (synchronous peripheral interface) Figure 47. SPI interface, master mode only INTR to 8032 PERIPH_CLK (f OSC ) 8 24.5 SPI configuration The SPI interface is reset by the MCU reset, and firmware needs to initialize the SFRs SPICON0, SPICON1, ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 16, 20, all the way up to 252. For example, if SPICLKD contains 24h, SPICLK has the frequency of PERIH_CLK divided by 36 decimal. The SPICLK frequency must be set low enough to allow the MCU ...
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SPI (synchronous peripheral interface) Table 90. SPICON0 register bit definition (continued) Bit Symbol 3 SSEL 2 FLSB 1 SPO 0 – Table 91. SPICON1: SPI interface control register 1 (SFR D7h, reset value 00h) Bit 7 Bit 6 – – ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 94. SPICLKD register bit definition Bit Symbol 7 DIV128 6 DIV64 5 DIV32 4 DIV16 3 DIV8 2 DIV4 1-0 Not Used Table 95. SPISTAT: SPI interface status register (SFR D3h, reset value 02h) Bit ...
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USB interface 25 USB interface UPSD34xx devices provide a full speed USB (Universal Serial Bus) device interface. The serial interface engine (SIE) provides the interface between the CPU and the USB (see Figure 48). Note: 1 For a list of ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 48. USB module block diagram D– USB– D+ USB+ 25.1 Basic USB concepts The Universal Serial Bus (USB) is more complex than the standard serial port and requires familiarity with the specification to fully understand ...
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USB interface 25.1.2 Endpoints Each USB device contains a collection of independent endpoints, with an endpoint being the destination of a communication flow between client software and the device. By design, each USB device’s endpoints are given specific unique identifiers ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 The data packet contains a DATA1 or DATA0 PID USB system, the host or device that is sending data is responsible for toggling the data PID between DATA0 and DATA1. The receiving device keeps ...
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USB interface 25.2 Types of transfers The USB specification defines four types of transfers, Bulk, Interrupt, Isochronous, and Control. Note: The UPSD34xx supports all types of transfers except Isochronous. ● Bulk Transfers (see Bulk data is transferred in both directions ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 51. Interrupt transfer IN ADDR ● Control Transfers (see Control transfers are used to configure and send commands to a device. Control transfers consist of two or three stages: – SETUP This stage always consists ...
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USB interface Figure 52. Control transfer SETUP ADDR Token packet IN ADDR Token packet OUT ADDR Token packet 25.3 Endpoint FIFOs The UPSD34xx’s USB module includes 5 endpoints and 10 FIFOs. Each endpoint has two FIFOs with one for IN ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 98. UPSD34xx supported endpoints Endpoint 0 Control 0 Control 1 Bulk/Interrupt OUT 1 Bulk/Interrupt IN 2 Bulk/Interrupt OUT 2 Bulk/Interrupt IN 3 Bulk/Interrupt OUT 3 Bulk/Interrupt IN 4 Bulk/Interrupt OUT 4 Bulk/Interrupt In 25.3.3 FIFO ...
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USB interface Figure 53. FIFOs with no pairing Serial interface engine ● Pairing FIFOs example Now assume that IN Endpoint1 and Endpoint2 FIFOs are paired for double buffering and the same 1024 bytes of data are to be transferred to ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 54. FIFO pairing example (1/2 IN paired and 3/4 OUT paired) Serial interface engine 25.3.4 Reading and writing FIFOs There are a total of ten 64-byte FIFOs. Each of the five Endpoints has two FIFOs, ...
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USB interface 25.3.6 Accessing the setup command buffer Setup Packets are sent from the host to a device’s Endpoint0 and consist of 8 bytes of command data. When the SIE receives a Setup packet from the host, it stores the ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 99. UPSD34xx USB SFR register map SFR SFR addr name 7 (hex) E8 UIF0 GLF E9 UIF1 – EA UIF2 – EB UIF3 – EC UCTL – ED USTA – USEL DIR F1 ...
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USB interface 25.4.2 Endpoint FIFO pairing Endpoint FIFOs can be paired for double buffering to provide an efficient method for bulk data transfers. With double buffering enabled, the MCU can operate on one data packet while another is being transferred ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 25.4.3 USB interrupts There are many USB related events that generate an interrupt. The events that generate an interrupt are selectively enabled through the use of the USB interrupt enable registers. All USB interrupts are serviced ...
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USB interface Table 105. UIE0 register bit definition Bit Symbol 7 – 6 – 5 – 4 – 3 RSTIE SUSPEND EOPIE 0 RESUMIE ● USB IN FIFO interrupt enable register (UIE1) When an endpoint’s IN FIFO ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 109. UIE2 register bit definition Bit Symbol OUT4IE 3 OUT3IE 2 OUT2IE 1 OUT1IE 0 OUT0IE ● USB IN FIFO NAK interrupt enable register (UIE3) When an endpoint’s IN FIFO is ...
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USB interface ● USB global interrupt flag register (UIF0) There are many different events that generate a USB interrupt requiring a number of registers to indicate the cause of the interrupt. To more efficiently identify the cause of the interrupt, ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 ● USB IN FIFO interrupt flag (UIF1) The USB IN FIFO Interrupt Flag register (see when an IN Endpoint FIFO that was full becomes empty. Once set, firmware must clear the flag by writing a '0' ...
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USB interface ● USB OUT FIFO interrupt flag (UIF2) The USB OUT FIFO Interrupt Flag register (see when an OUT Endpoint FIFO that was empty becomes full. Once set, firmware must clear the flag by writing a '0' to the ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 ● USB IN FIFO NAK interrupt flag (UIF3) The USB IN FIFO NAK Interrupt Flag register (see indicate when an IN Endpoint FIFO is not ready. The Endpoint FIFO is not ready when data has not ...
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USB interface ● USB control register (UCTL) The USB control register (see FIFOs visible in the XDATA space and for generating a remote wakeup signal. Upon a reset, the USB module is disabled and must be enabled by the CPU ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 ● USB endpoint0 status (USTA) The USB Endpoint0 Status register (see occur on the USB that are directed to endpoint0. Table 122. USB endpoint0 status (USTA 0EDh, reset value 00h) Bit 7 Bit 6 – – ...
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USB interface ● USB endpoint select register (USEL) Endpoints share the same XDATA space for FIFOs as well as the same SFR addresses for Control and FIFO Valid Size registers. The USB endpoint select register (see Table 124) is used ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 ● USB endpoint control register (UCON) The Endpoint selected by the USB endpoint select register (see page 172) determines the direction and FIFO (IN or OUT) that is controlled by the USB endpoint control register (see ...
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USB interface Table 127. UCON register bit definition (continued) Bit Symbol 0 BSY ● USB FIFO valid size (USIZE) The Endpoint selected by the USB endpoint select register (see page 172) determines the direction and FIFO that is controlled by ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 ● USB FIFO base address high and low registers (UBASEH and UBASEL) All 10 Endpoint FIFOs share the same 64-byte address range. The 16-bit base address for the FIFOs is specified using the USB base address ...
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USB interface ● USB setup command index and value registers (USCI and USCV) When a Setup/Data packet is received over the USB, the 8 bytes of data received are stored in a command buffer. The USB setup command index register ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 25.5 Typical connection to USB Connecting the UPSD34xx to the USB is simple and straightforward. typical self-powered example requiring only three resistors and a USB power detection circuit. The USB power detection circuit detects when the ...
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Analog-to-digital convertor (ADC) 26 Analog-to-digital convertor (ADC) The ADC unit in the UPSD34xx is a SAR type ADC with an SAR register, an auto-zero comparator and three internal DACs. The unit has 8 input channels with 10-bit resolution. The A/D ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 56. 10-bit ADC AV REF AV REF P1.0 ADC0 P1.1 ADC1 P1.2 ADC2 P1.3 ADC3 P1.4 ADC4 P1.5 ADC5 P1.6 ADC6 P1.7 ADC7 Table 138. ACON register (SFR 97h, reset value 00h) Bit 7 Bit ...
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Analog-to-digital convertor (ADC) Table 139. ACON register bit definition (continued) Bit Symbol 1 ADST 0 ADSF Table 140. ADCPS register details (SFR 94h, Reset Value 00h) Bit Symbol 7:4 – 3 ADCCE 2:0 ADCPS[2:0] Table 141. ADAT0 register (SFR 95h, ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 27 Programmable counter array (PCA) with PWM There are two Programmable Counter Array blocks (PCA0 and PCA1) in the UPSD34xx. A PCA block consists of a 16-bit up-counter, which is shared by three TCM (Timer Counter ...
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Programmable counter array (PCA) with PWM Table 143. PCA0 and PCA1 registers SFR address PCA0 PCA1 A9, BD, AA, BE ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 144. CCON2 register bit definition (SFR 0FBh, reset value 10h) Bit 7 Bit 6 – – Table 145. CCON2 register bit definition Bit Symbol 4 PCA0CE PCA0PS 3:0 [3:0] Table 146. CCON3 register bit definition ...
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Programmable counter array (PCA) with PWM 27.6 Toggle mode In this mode, the user writes a value to the TCM's CAPCOM registers and enables the comparator. When there is a match with the Counter output, the output of the TCM ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 59. PWM mode - (x8), fixed frequency OVERFLOW 27.8 PWM mode - (x8), programmable frequency In ...
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Programmable counter array (PCA) with PWM Figure 60. PWM mode - (x8) programmable frequency PWM FREQ COMPARE PWMFm PWMFm = PCACLm PCACHm ENABLE 8-bit COMPARATORm ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 27.10 PWM mode - fixed frequency, 10-bit The 10-bit PWM logic requires that all 3 TCMs in PCA0 or PCA1 operate in the same 10-bit PWM mode. The 10-bit PWM operates in a similar manner as ...
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Programmable counter array (PCA) with PWM Table 149. PCA0 register bit definition (continued) Bit Symbol 3 – 2 10B_PWM CLK_SEL 1-0 [1:0] Table 150. PCA1 control register PCACON1 (SFR 0BCh, reset value 00h) Bit 7 Bit 6 – EN_PCA Table ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 153. PCASTA register bit definition (continued) Bit Symbol 5 INTF4 4 INTF3 3 OVF0 2 INTF2 1 INTF1 0 INTF0 27.13 TCM interrupts There are 8 TCM interrupts: 6 match or capture interrupts and two ...
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Programmable counter array (PCA) with PWM Table 155. TCMMODE0 - TCMMODE5 register bit definition (continued) Bit Symbol 2 TOGGLE 1-0 PWM[1:0] Table 156. TCMMODE register configurations EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 28 PSD module The PSD module is stacked with the MCU module to form the UPSD34xx, see Hardware description on page two separate modules interface with each other at the 8032 Address, Data, and Control interface ...
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PSD module 28.1 PSD module functional description Major functional blocks are shown in each major block. 28.1.1 8032 address/data/control interface These signals attach directly to the MCU module to implement a 16-bit multiplexed 8051- style bus between the two stacked ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 28.1.4 Secondary Flash memory The smaller Secondary Flash memory is also divided into equal sized sectors that are individually selectable by the Decode PLD signals, named CSBOOTx, one signal for each Secondary Flash memory sector. Each ...
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PSD module page register (Figure registers. Page register outputs feed directly into both PLDs creating extended address signals used to “page” memory beyond the 64K byte limit (program space or XDATA). Most 8051 compilers directly support memory paging, also known ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 have direct connection to the 8032 data bus allowing them to be loaded and read directly by the 8032 at runtime through OMC registers in csiop. This direct access is good for making small peripheral devices ...
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... Port C, TSTAT and TERR, in addition to TMS, TCK, TDI and TDO, and this is referred to as “6-pin JTAG”. The FlashLINK JTAG programming cable is available from STMicroelectronics and PSDsoft Express software is available at no charge from www.st.com/psm. More JTAG ISP information maybe found in JTAG debug on page The MCU module is also included in the JTAG chain within the UPSD34xx device for 8032 debugging and emulation ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 28.1.16 Power management The PSD module has bits in csiop registers that are configured at run-time by the 8032 to reduce power consumption of the GPLD. The Turbo Bit in the PMMR0 register can be set ...
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PSD module 28.2.1 8032 program address space In the example of three memory pages in the upper half of program address space, and the remaining two sectors of Main Flash memory (fs0, fs1) reside in the lower half of program ...
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UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 159. HDL statement example generated from PSDsoft express for memory map = ((address ≥ ^h0000) & (address ≤ ^h1FFF)); rs0 = ((address ≥ ^h2000) & (address ≤ ^h20FF)); csiop = ((address ≥ ^h0000) & (address ...
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PSD module maintained by alternating between the two flash sectors. For example, a data set of 128 bytes is written and maintained by software in a distributed fashion across one 8 Kbyte sector of Secondary Flash memory until it becomes ...