UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 298

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

Important notes
34.12
34.13
298/300
Incorrect code execution when code banks are switched
Description
When a code bank is switched, the PFQ/BC contain values from the previously selected
bank and are not automatically flushed and reloaded from the newly selected code bank.
Impact on application
Depending on the contents of the PFQ/BC when the code bank is switched, improper code
execution may result.
Workaround
The PFQ/BC must be flushed when the code bank is changed. Disabling and re-enabling
the PFQ/BC will flush them. The following instructions are an example of how to flush the
PFQ/BC:
ANL
ORL
Bank switching is typically handled by tool vendors in a file called l51_bank.a51. The uPSD
tools offered by Keil and Raisonance now include an updated version of l51_bank.a51 for
the uPSD products that flushes the PFQ/BC. The most recent banking examples available
from ST's website include the updated l51_bank.a51 files.
9
Description
If the 9th transmit data bit is written by firmware into TB8 at the same time as a received 9th
bit is being written by the hardware into RB8, RB8 is not correctly updated. This applies to
both UART0 and UART1. Typically, the 9th data bit is used as a parity bit to check for data
transmission errors on a byte by byte basis.
Impact on application
UART Modes 2 and 3 can't be used reliably in full-duplex mode.
Workaround
Revision A and B - Some options include:
1.
2.
3.
4.
th
Only use Mode 1 (8 data bits) for full-duplex communication.
Use Mode 1 and a packet based communication protocol with a checksum or CRC to
detect data transmission errors.
Use UART0 in mode 2 or 3 for transmitting data and UART1 in mode 2 or 3 for
receiving data.
Use some form of handshaking to ensure that data is never transmitted and received
simultaneously on a single UART configured in mode 2 or 3.
received data bit corrupted in UART modes 2 and 3
BUSCON,#03Fh
BUSCON,#0C0h
;Disable PFQ/BC
;Enable PFQ/BC
UPSD3422, UPSD3433, UPSD3434, UPSD3454