UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 257

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
Table 203. Function status during power-up reset, warm reset, power-down mode (continued)
1. VM register Bit 7 (PIO_EN) and Bit 0 (SRAM in 8032 program space) are cleared to zero at power-up and warm reset
28.6.1
28.6.2
All other csiop registers
Port configuration or
conditions.
VM register
register
JTAG ISP and JTAG debug
An IEEE 1149.1 serial JTAG interface is used on UPSD34xx devices for ISP (in-system
programming) of the PSD module, and also for debugging firmware on the MCU module.
IEEE 1149.1 Boundary Scan operations are not supported in the UPSD34xx.
The main advantage of JTAG ISP is that a blank UPSD34xx device may be soldered to a
circuit board and programmed with no involvement of the 8032, meaning that no 8032
firmware needs to be present for ISP. This is good for manufacturing, for field updates, and
for easy code development in the lab. JTAG-based programmers and debuggers for
UPSD34xx are available from STMicroelectronics and 3rd party vendors.
ISP is different than IAP (in-application programming). IAP involves the 8032 to program
Flash memory over any interface supported by the 8032 (e.g., UART, SPI, I2C), which is
good for remote updates over a communication channel. UPSD34xx devices support both
ISP and IAP. The entire PSD module (Flash memory and PLD) may be programmed with
JTAG ISP, but only the Flash memories may be programmed using IAP.
JTAG chaining inside the package
JTAG protocol allows serial “chaining” of more than one device in a JTAG chain. The
UPSD34xx is assembled with a stacked die process combining the PSD module (one die)
and the MCU module (the other die). These two die are chained together within the
UPSD34xx package. The standard JTAG interface has four basic signals:
●
●
●
●
Every device that supports IEEE 1149.1 JTAG communication contains a test access port
(TAP) controller, which is a small state machine to manage JTAG protocol and serial
streams of commands and data. Both the PSD module and the MCU module each contain a
TAP controller.
Figure 90
equipment will connect externally to the four IEEE 1149.1 JTAG pins on Port C. The TDI pin
on the UPSD34xx package goes directly to the PSD module first, then exits the PSD module
through TDO. TDO of the PSD module is connected to TDI of the MCU module. The serial
path is completed when TDO of the MCU module exits the UPSD34xx package through the
TDO pin on Port C. The JTAG signals TCK and TMS are common to both modules as
specified in IEEE 1149.1. When JTAG devices are chained, typically one devices is in
BYPASS mode while another device is executing a JTAG operation. For the UPSD34xx, the
(1)
TDI - Serial data into device
TDO - Serial data out of device
TCK - Common clock
TMS - Mode Selection
illustrates how these die are chained within a package. JTAG programming/test
was specified in PSDsoft
Initialized with value that
Power-up reset
Cleared to 00h
was specified in PSDsoft
Initialized with value that
Cleared to 00h
Warm reset
APD Power-down mode
Unchanged
Unchanged
PSD module
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