UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 207

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.5
28.5.1
Table 162. CSIOP registers and their offsets (in hexadecimal) (continued)
PSD module detailed operation
Specific details are given here for the following key functional areas on the PSD module:
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Flash memory operation
The Flash memories are accessed through the 8032 Address, Data, and Control Bus
interfaces. Flash memories (and SRAM) cannot be accessed by any other bus master other
than the 8032 MCU (these are not dual-port memories).
The 8032 cannot write to Flash memory as it would an SRAM (supply address, supply data,
supply WR strobe, assume the data was correctly written to memory). Flash memory must
first be “unlocked” with a special instruction sequence of byte WRITE operations to invoke
an internal algorithm inside either Flash memory array, then a single data byte is written
(programmed) to the Flash memory array, then programming status is checked by a byte
READ operation or by checking the Ready/Busy pin (PC3).
of the special instruction sequences to program a byte to either of the Flash memory arrays,
erase the arrays, and check for different types of status from the arrays.
PMMR0
PMMR2
PMMR3
Page
VM (Virtual
Memory)
Register
name
Flash Memories
PLDs (DPLD and GPLD)
I/O Ports
Power Management
JTAG ISP and Debug Interface
(80-pin)
Port A
Port B Port C Port D Other
B0h
B4h
C7h
E0h
E2h
Power management register 0.
WRITE and READ.
Power management register 2.
WRITE and READ.
Power management register 3.
WRITE and READ. However,
Bit 1 can be cleared only by a
reset condition.
Memory page register. WRITE
and READ.
Places PSD module memories
into 8032 Program Address
Space and/or 8032 XDATA
Address Space. (VM overrides
initial non-volatile setting that
was specified in PSDsoft
Express. Reset restores initial
setting)
Table 163 on page 209
Description
PSD module
Table 200
Table 201
Table 202
Table 160
page 249
page 249
page 250
page 194
page 203
Table 62
lists all
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