UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 149

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
Table 94.
Table 95.
Table 96.
Bit 7
1-0
7-5
Bit
Bit
7
6
5
4
3
2
–
4
3
2
1
0
SPICLKD register bit definition
Not Used
SPISTAT: SPI interface status register (SFR D3h, reset value 02h)
SPISTAT register bit definition
RORISF
Symbol
Symbol
DIV128
DIV64
DIV32
DIV16
TEISF
BUSY
DIV8
DIV4
RISF
Bit 6
TISF
–
–
Bit 5
R/W
R/W
RW
RW
RW
RW
RW
RW
R
R
R
R
R
–
–
–
0 = No division
1 = Divide f
0 = No division
1 = Divide f
0 = No division
1 = Divide f
0 = No division
1 = Divide f
0 = No division
1 = Divide f
0 = No division
1 = Divide f
Reserved
SPI Busy
0 = Transmit or Receive is completed
1 = Transmit or Receive is in process
Transmission End Interrupt Source flag
0 = Automatically resets to '0' when firmware reads this
register
1 = Automatically sets to '1' when transmission end occurs
Receive Overrun Interrupt Source flag
0 = Automatically resets to '0' when firmware reads this
register
1 = Automatically sets to '1' when receive overrun occurs
Transfer Interrupt Source flag
0 = Automatically resets to '0' when SPITDR is full (just after
the SPITDR is written)
1 = Automatically sets to '1' when SPITDR is empty (just after
byte loads from SPITDR into SPI shift register)
Receive Interrupt Source flag
0 = Automatically resets to '0' when SPIRDR is empty (after
the SPIRDR is read)
1 = Automatically sets to '1' when SPIRDR is full
BUSY
Bit 4
OSC
OSC
OSC
OSC
OSC
OSC
TEISF
clock by 128
clock by 64
clock by 32
clock by 16
clock by 8
clock by 4
Bit 3
SPI (synchronous peripheral interface)
Definition
Definition
RORISF
Bit 2
TISF
Bit 1
RISF
Bit 0
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