UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 159

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
25.3.4
25.3.5
Figure 54. FIFO pairing example (1/2 IN paired and 3/4 OUT paired)
Reading and writing FIFOs
There are a total of ten 64-byte FIFOs. Each of the five Endpoints has two FIFOs, one IN
FIFO for IN transactions and one OUT FIFO for OUT transactions. The FIFOs are
accessible by the CPU through a 64-byte segment in the XDATA space when the VISIBLE
Bit is set (see
accessible by the CPU but are still accessible by the SIE. The base address of the 64-byte
segment is specified by the USB base address high register (see
and the USB base address low register (see
is set, the FIFO that is accessible in the 64-byte XDATA space segment is the FIFO selected
by the USEL register. The USEL register contains two fields used for selecting the
accessible FIFO. The EP field determines the Endpoint selected and the DIR Bit selects the
IN or OUT FIFO associated with the Endpoint.
Accessing FIFO control registers, UCON, and USIZE
Each of the 10 Endpoint FIFOs has an associated USB endpoint control register (UCON,
0F1H) and a USB FIFO valid size register (USIZE, 0F2H). The USB endpoint select register
(USEL) is not only used to select the Endpoint FIFO that is accessible in the XDATA space,
but also selects the associated Endpoint’s UCON and USIZE registers that are accessible at
SFR addresses 0F1H and 0F2H.
interface
engine
Serial
Table 120 on page
(not available)
(not available)
Endpoint0
Endpoint1
Endpoint2
Endpoint3
Endpoint4
Endpoint3
Endpoint2
Endpoint1
Endpoint0
Endpoint4
P
a
e
d
P
a
e
d
i
r
i
r
Endpoint0 OUT FIFO
Endpoint1 OUT FIFO
Endpoint2 OUT FIFO
Endpoint3 OUT FIFO
Endpoint4 OUT FIFO
Endpoint4 IN FIFO
Endpoint3 IN FIFO
Endpoint2 IN FIFO
Endpoint1 IN FIFO
Endpoint0 IN FIFO
170). If the VISIBLE Bit is not set, the FIFOs are not
Table 132 on page
P
P
a
e
d
a
e
d
r
r
i
i
(not available)
(not available)
Endpoint2
Endpoint0
Endpoint1
Endpoint2
Endpoint3
Endpoint4
Endpoint4
Endpoint3
Endpoint1
Endpoint0
interface
FIFO
logic
175). When the VISIBLE Bit
Table 130 on page
XDATA
CTRL
USB interface
USB SFRs
MCU
8032
AI10494b
159/300
175)
R
S
F
b
u
s