UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 223

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.5.28
Figure 74. DPLD logic array
General PLD (GPLD)
The GPLD is used to create general system logic.
architecture of the entire GPLD, and
one OMC, one IMC, and one I/O port pin, which is representative of pins on Ports A, B, and
C. It is important to understand how these elements work together. A more detailed
description will follow for the three major blocks (OMC, IMC, I/O Port) shown in
Figure 75
The GPLD contains:
●
●
●
●
●
●
AI06601b
OMC feedback (MCELLBC.FB0-7)
8032 CNTL (RD, WR, PSEN, ALE)
OMC feedback (MCELLAB.FB0-7)
Flash memory prog status (RDYBSY)
16 Output Macrocells (OMC)
20 Input Macrocells (IMC)
OMC Allocator
Product Term Allocator inside each OMC
AND-OR Array capable of generating up to 137 product terms
Three I/O Ports, A, B, and C
Pin input ports A, B, C (IMCs)
Page register (PGR0 - PGR7)
Power-down indicator (PDN)
8032 address (A0 - A15)
PSM module reset (RST)
Pin input port D
PLD input bus
also shows which csiop registers to access for various PLD and I/O functions.
16
20
4
1
1
2
8
8
8
1
Figure 75 on page 224
Figure 73 on page 221
shows the relationship between
product terms
Number of
3
3
3
3
3
3
3
3
3
3
3
3
2
1
1
1
1
1
CSBOOT0
CSBOOT1
CSBOOT2
CSBOOT3
shows the
CSIOP
PSEL0
PSEL1
ECS1
ECS0
RS0
FS0
FS1
FS2
FS3
FS4
FS5
FS6
FS7
PSD module
Figure
I/O & control
registers
memory
Secondary
External
Selects
SRAM
Select
(Port D)
Peripheral
Select
Selects
I/O mode
sector
Flash
memory
Chip-
Main
Selects
Selects
sector
range
Flash
223/300
75.