UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 230

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

PSD module
230/300
signal to latch the incoming signal. Then define an equation for the IMC clock (.ld) or the
IMC gate (.le) signal in the “I/O Equations” section.
If the user would like to latch an incoming signal using the gate signal ALE from the 8032,
then in PSDsoft Express, for a given input pin on Port A, B, or C, specify “Latched Address”
as the pin function.
If it is desired to pass an incoming signal through an IMC directly to the AND-OR array
inputs without clocking or gating (this is most common), in PSDsoft Express simply specify
“Logic or Address” for the input pin function on Port A, B, or C.
Figure 78. Detail of a single IMC
Table 173. Input macrocell port A
1. Port A not available on 52-pin UPSD34xx devices.
2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’.
Table 174. Input macrocell port B (address = csiop + offset 0Bh)
1. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’.
Table 175. Input macrocell port C (address = csiop + offset 18h)
1. X = Not guaranteed value, can be read either '1' or '0.' These are JTAG pins.
2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’.
IMC PC7
IMC PB7
IMC PA7
Bit 7
Bit 7
Bit 7
From AND-OR array
To PLD input bus
IMC PB6
IMC PA6
Bit 6
Bit 6
Bit 6
X
IMC PB5
IMC PA5
ALE
8032 read of particular CSIOP IMC register
8032 data bit
Bit 5
Bit 5
Bit 5
PT clock or gate (.LD OR .LE)
X
This signal is ganged to 3 other
IMCs, grouping IMC 0 - 3 or IMC 4 - 7.
IMC PC4
IMC PB4
IMC PA4
(1)
PSDsoft
Bit 4
Bit 4
Bit 4
(address = csiop + offset 0Ah)
UPSD3422, UPSD3433, UPSD3434, UPSD3454
M
U
X
ALE
Pin input
Latched input
Gated input
IMC PC3
IMC PB3
IMC PA3
PSDsoft
Bit 3
Bit 3
Bit 3
M
U
X
Input macrocell (IMC)
IMC PC2
IMC PB2
IMC PA2
Q
Q
(.LD)
(.LE)
Bit 2
Bit 2
Bit 2
D
G
D
(1) (2)
(1)
IMC PB1
IMC PA1
(2)
Bit 1
Bit 1
Bit 1
X
Input signal
from pin on
port A, B, or C
From I/O port
logic
AI06603b
IMC PB0
IMC PA0
Bit 0
Bit 0
Bit 0
X