UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 195

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.1.11
28.1.12
28.1.13
Note:
28.1.14
have direct connection to the 8032 data bus allowing them to be loaded and read directly by
the 8032 at runtime through OMC registers in csiop. This direct access is good for making
small peripheral devices (shifters, counters, state machines, etc.) that are accessed directly
by the 8032 with little overhead. There are 69 GPLD inputs which include: 8032 address and
control signals, page register outputs, PSD module Port pin inputs, and GPLD feedback.
OMCs
There are two banks of eight OMCs inside the GPLD, MCELLAB, and MCELLBC, totalling
16 OMCs all together. Each individual OMC is a base logic element consisting of a flip-flop
and some AND-OR logic
OMCs is similar in nature to a 22V10 PLD device with the familiar sum-of-products (AND-
OR) construct. True and compliment versions of 69 input signals are available to the inputs
of a large AND-OR array. AND-OR array outputs feed into an OR gate within each OMC,
creating up to 10 product-terms for each OMC. Logic output of the OR gate can be passed
on as combinatorial logic or combined with a flip-flop within in each OMC to realize
sequential logic. OMC outputs can be used as a buried nodes driving internal feedback to
the AND-OR array, or OMC outputs can be routed to external pins on Ports A, B, or C
through the OMC Allocator.
OMC allocator
The OMC allocator
pins on either Port A or Port B, and will route eight of the OMCs from MCELLBC to pins on
either Port B or Port C, based on what is specified in PSDsoft Express.
IMCs
Inputs from pins on Ports A, B, and C are routed to IMCs for conditioning (clocking or
latching) as they enter the chip, which is good for sampling and debouncing inputs.
Alternatively, IMCs can pass port input signals directly to PLD inputs without clocking or
latching
through IMC registers in csiop.
The JTAG signals TDO, TDI, TCK, and TMS on Port C do not route through IMCs, but go
directly to JTAG logic.
I/O ports
For 80-pin UPSD34xx devices, the PSD module has 22 individually configurable I/O pins
distributed over four ports (these I/O are in addition to I/O on MCU module). For 52-pin
UPSD34xx devices, the PSD module has 13 individually configurable I/O pins distributed
over three ports. See
packages.
I/O port pins on the PSD module (Ports A, B, C, and D) are completely separate from the
port pins on the MCU module (Ports 1, 3, and 4). They even have different electrical
characteristics. I/O port pins on the PSD module are accessed by csiop registers, or they
are controlled by PLD equations. Conversely, I/O Port pins on the MCU module are
controlled by the 8032 SFR registers.
(Figure 78 on page
(Figure 77 on page
Figure 84 on page 243
(Figure 76 on page
230). The 8032 may read the IMCs asynchronously at any time
227) will route eight of the OMCs from MCELLAB to
226). The general structure of the GPLD with
for I/O port pin availability on these two
PSD module
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