UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 129

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
23.8
I
Table 75.
Table 76.
2
C interface control register (S1CON)
Bit 7
CR2
1, 0
Bit
7
6
5
4
3
2
CR1, CR0
Serial control register S1CON (SFR DCh, reset value 00h)
S1CON register bit definition
Symbol
ADDR
ENI1
ENI1
Bit 6
CR2
STO
STA
AA
Bit 5
R/W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
STA
This bit, along with bits CR1 and CR0, determine the SCL
clock frequency (f
bits create a clock divisor for f
I
0 = SIOE disabled, 1 = SIOE enabled. When disabled, both
SDA and SCL signals are in high impedance state.
START flag.
When set, Master mode is entered and SIOE generates a
Start condition only if the I
condition is detected on the bus, the STA flag is cleared by
hardware. When the STA bit is set during an interrupt service,
the Start condition will be generated after the interrupt service.
STOP flag
When STO is set in Master mode, the SIOE generates a Stop
condition. When a Stop condition is detected, the STO flag is
cleared by hardware. When the STO bit is set during an
interrupt service, the Stop condition will be generated after the
interrupt service.
This bit is set when an address byte received in Slave mode
matches the device address programmed into the S1ADR
register. The ADDR bit must be cleared with firmware.
Assert Acknowledge enable
If AA = 1, an acknowledge signal (low on SDA) is automatically
returned during the acknowledge bit-time on the SCL line
when any of the following three events occur:
1.
2.
3.
When AA = 0, no acknowledge is returned (high on SDA
during acknowledge bit-time).
These bits, along with bit CR2, determine the SCL clock
frequency (f
create a clock divisor for f
2
C Interface Enable
Bit 4
STO
SIOE in Slave mode receives an address that
matches contents of S1ADR register
A data byte has been received while SIOE is in
Master Receiver mode
A data byte has been received while SIOE is a
selected Slave Receiver
SCL
ADDR
) when SIOE is in Master mode. These bits
Bit 3
SCL
) when SIOE is in Master mode. These
OSC
2
Function
C bus is not busy. When a Start
Bit 2
. See
AA
OSC
. See
Table 77
Table
Bit 1
for values.
77.
CR[1:0]
I
2
C interface
Bit 0
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