UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 250

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

PSD module
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Table 201. Power management mode register PMMR2 (address = csiop + offset
1. All the bits of this register are cleared to zero following power-up. Subsequent Reset (RST) pulses do not
2. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.
Table 202. Power management mode register PMMR3 (address = csiop + offset
1. All the bits of this register are cleared to zero following power-up. Subsequent Reset (RST) pulses do not
Automatic power-down (APD)
The APD unit shown in
by monitoring the activity of the 8032 Address Latch Enable (ALE) signal. If the APD unit is
enabled by writing a logic ’1’ to Bit 1 of the csiop PMMR0 register, and if ALE signal activity
has stopped (8032 in sleep mode), then the four-bit APD counter starts counting up. If the
ALE signal remains inactive for 15 clock periods of the CLKIN signal (pin PD1), then the
APD counter will reach maximum count and the power down indicator signal (PDN) goes to
logic ’1’ forcing the PSD module into power-down mode. During this time, all buffers on the
PSD module for 8032 address and data signals are disabled in silicon, preventing the PSD
module Flash memories from waking up from standby mode, even if noise or other devices
Bit 3-
Bit 3
Bit 4
Bit 5
Bit 5
Bit 7
Bit 0
Bit 1 FORCE_PD
7
clear the registers.
clear the registers.
Blocking Bit,
Blocking Bit,
Blocking Bit,
Blocking Bit,
PSEN to
PLDs
PLDs
PLDs
PLDs
PC7 to
ALE to
RD to
X
X
X
B4h)
C7h)
(2)
(2)
(2)
(2)
(1)
(1)
(continued)
0 =
1 =
0 =
1 =
0 =
1 =
0 =
1 =
0 =
1 =
on
off
on
off
on
off
on
off
off
on
0
0
0
Figure 73 on page 221
8032 RD input to the PLD Input Bus is not blocked.
8032 RD input to PLD Input Bus is blocked, saving power.
8032 PSEN input to the PLD Input Bus is not blocked.
8032 PSEN input to PLD Input Bus is blocked, saving power.
8032 ALE input to the PLD Input Bus is not blocked.
8032 ALE input to PLD Input Bus is blocked, saving power.
Pin PC7 input to the PLD Input Bus is not blocked.
Pin PC7 input to PLD Input Bus is blocked, saving power.
Not used, and should be set to zero.
Not used, and should be set to zero.
APD counter will cause Power-Down Mode if APD is enabled.
Power-Down mode will be entered immediately regardless of APD
activity.
Not used, and should be set to zero.
UPSD3422, UPSD3433, UPSD3434, UPSD3454
puts the PSD module into power-down mode