UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 74

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

Power saving modes
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Table 31.
1. The Watchdog Timer is not active during Idle mode. Other supervisor functions are active: LVD, external
Table 32.
Table 33.
Table 34.
Power-down
Power-
SMOD0
Mode
down
Idle
reset, JTAG Debug reset.
Bit 7
Mode
Bit
Idle
7
6
5
4
3
2
Ports 1, 3, 4
Maintain
Maintain
MCU module port and peripheral status during reduced power modes
State of 8032 MCU bus signals during power-down and idle modes
PCON: power control register (SFR 87h, reset value 00h)
PCON register bit definition
Symbol
SMOD1
SMOD0
SMOD1
RCLK1
TCLK1
data
data
Bit 6
POR
–
ALE
0
0
UART0,1
SPI, I
Disabled
Active
Bit 5
R/W
R,W
R,W
R,W
R,W
R,W
–
–
2
PSEN_
C,
1
1
Baud Rate Double Bit (UART0)
0 = No doubling
1 = Doubling
(See
Baud Rate Double Bit for 2nd UART (UART1)
0 = No doubling
1 = Doubling
(See
Reserved
Only a power-on reset sets this bit (cold reset). Warm reset
will not set this bit.
0 = Cleared to zero with firmware
1 = Is set only by a power-on reset generated by Supervisory
circuit (see
details).
Received Clock Flag (UART1)
(See
Transmit Clock Flag (UART1)
(See
Disabled
Timer
Active
PCA,
0,1,2
POR
Bit 4
Section 21.3: UART baud rates on page 110
Section 21.3: UART baud rates on page 110
Table 60 on page 101
Table 60 on page 101
UPSD3422, UPSD3433, UPSD3434, UPSD3454
RD_
1
1
Section 19.3: Power-up reset on page 92
Disabled
Active
USB
RCLK1
Bit 3
WR_
Disabled
Active
1
1
Function
ADC
TCLK1
for flag description.)
for flag description)
Bit 2
Disabled
INT0,1
AD0-7
Active
EXT
FFh
FFh
Bit 1
PD
Supervisory
for details.)
for details.)
Disabled
Active
A8-15
for
FFh
FFh
Bit 0
IDL
(1)