UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 255

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.5.60
28.5.61
28.5.62
28.6
PLD blocking bits
Blocking specific signals from entering the PLDs using bits of the csiop PMMR registers can
further reduce PLD AC current consumption by lowering the effective composite frequency
of inputs to the PLDs.
Blocking 8032 bus control signals
When the 8032 is active on the MCU module, four bus control signals (RD, WR, PSEN, and
ALE) are constantly transitioning to manage 8032 bus traffic. Each time one of these signals
has a transition from logic ’1’ to '0,' or 0 to '1,' it will wake up the PLDs if operating in non-
Turbo mode, or when in Turbo mode it will cause the affected PLD gates to draw current. If
equations in the DPLD or GPLD do not use the signals RD, WR, PSEN, or ALE then these
signals can be blocked which will reduce the AC current component substantially. These bus
control signals are rarely used in DPLD equations because they are routed in silicon directly
to the memory arrays of the PSD module, bypassing the PLDs. For example, it is NOT
necessary to qualify a memory chip select signal with an MCU write strobe, such as “fs0 =
address range & !WR_”. Only “fs0 = address range” is needed.
Each of the 8032 bus control signals may be blocked individually by writing to Bits 2, 3, 4,
and 5 of the PMMR2 register shown in
bus control signals only prevents them from reaching the PLDs, but they will always go to
the memories directly.
However, sometimes it is necessary to use these 8032 bus control signals in the GPLD
when creating interface signals to external I/O peripherals. But it is still possible to save
power by dynamically unblocking the bus signals before reading/writing the external device,
then blocking the signals after the communication is complete.
The user can also block an input signal coming from pin PC7 to the PLD input bus if desired
by writing to Bit 6 of PMMR2.
Blocking common clock, CLKIN
The input CLKIN (from pin PD1) can be blocked to reduce current consumption. CLKIN is
used as a common clock input to all OMC flip-flips, it is a general input to the PLD input bus,
and it is used to clock the APD counter. In PSDsoft Express, the function of pin PD1 must be
specified as “Common Clock Input, CLKIN” before programming the device with JTAG to get
the CLKIN function.
Bit 4 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the PLD input bus, but
CLKIN will still reach the APD counter.
Bit 5 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the OMC flip-flops only,
but CLKIN is still available to the PLD input bus and the APD counter.
See
PSD module reset conditions
The PSD module receives a reset signal from the MCU module. This reset signal is referred
to as the “RST” input in PSD module documentation, and it is active-low when asserted. The
character of the RST signal generated from the MCU module is described in
Supervisory functions on page
Table 200 on page 249
for details.
91.
Table 201 on page
249. Blocking any of these four
Section 19:
PSD module
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