UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 13

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
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BUSCON: bus control register (SFR 9Dh, reset value EBh) . . . . . . . . . . . . . . . . . . . . . . . 88
BUSCON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Number of MCU_CLK periods required to optimize bus transfer rate . . . . . . . . . . . . . . . . 90
WDKEY: Watchdog timer key register (SFR AEh, reset value 55h) . . . . . . . . . . . . . . . . . . 94
WDKEY register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
WDRST: Watchdog timer reset counter register (SFR A6h, reset value 00h) . . . . . . . . . . 94
WDRST register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TCON: Timer control register (SFR 88h, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . . . 97
TCON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TMOD: Timer mode register (SFR 89h, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . 99
TMOD register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
T2CON: Timer 2 control register (SFR C8h, reset value 00h) . . . . . . . . . . . . . . . . . . . . . 101
T2CON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Timer/counter 2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Commonly used baud rates generated from timer2
(T2CON = 34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
UART operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SCON0: serial port UART0 control register (SFR 98h, reset value 00h) . . . . . . . . . . . . . 109
SCON0 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SCON1: serial port UART1 control register (SFR D8h, reset value 00h) . . . . . . . . . . . . . 109
SCON1 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Commonly used baud rates generated from timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
IRDACON register bit definition (SFR CEh, reset value 0Fh). . . . . . . . . . . . . . . . . . . . . . 120
IRDACON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Baud rate selection register (SFR xxh, reset value xxh). . . . . . . . . . . . . . . . . . . . . . . . . . 120
Baud rate of UART#1 for IrDA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Recommended CDIV[4:0] values to generate SIRClk
(default CDIV[4:0] = 0Fh, 15 decimal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Serial control register S1CON (SFR DCh, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . 129
S1CON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Selection of the SCL frequency in Master mode based on f
S1STA: I
S1STA register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
S1DAT: I2C data shift register (SFR DEh, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . 132
S1DAT register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
S1ADR: I2C address register (SFR DFh, reset value 00h). . . . . . . . . . . . . . . . . . . . . . . . 132
S1ADR register bit definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
S1SETUP: I
S1SETUP register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Number of I
Start condition hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
S1SETUP examples for various I
frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SPICON0: control register 0 (SFR D6h, reset value 00h). . . . . . . . . . . . . . . . . . . . . . . . . 147
SPICON0 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SPICON1: SPI interface control register 1 (SFR D7h, reset value 00h) . . . . . . . . . . . . . . 148
SPICON1 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SPICLKD: SPI prescaler (clock divider) register (SFR D2h, reset value 04h) . . . . . . . . . 148
SPICLKD register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SPISTAT: SPI interface status register (SFR D3h, reset value 02h) . . . . . . . . . . . . . . . . 149
SPISTAT register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Types of packet IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
2
C interface status register (SFR DDh, reset value 00h) . . . . . . . . . . . . . . . . . . 130
2
2
C bus samples taken after 1-to-0 transition on SDA (Start condition) . . . . . 134
C Start condition sample setup register (SFR DBh, reset value 00h) . . . . . 133
2
C bus speeds and oscillator
OSC
examples . . . . . . . . . . . 130
List of tables
13/300