UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 279

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
Table 220. CPLD combinatorial timing (5 V PSD module)
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given
2. t
Table 221. CPLD combinatorial timing (3 V PSD module)
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given
2. t
Symbol
Symbol
t
t
t
ARPW
t
t
t
PD
ARPW
t
t
t
ARP
ARD
PD
t
amount.
ALE to CPLD combinatorial output (80-pin package only).
amount.
ALE to CPLD combinatorial output (80-pin package only).
t
t
ARP
ARD
EA
ER
PD
PD
EA
ER
(2)
(2)
for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and
for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and
CPLD input pin/feedback to
CPLD combinatorial output
CPLD input to CPLD
Output Enable
CPLD input to CPLD
Output Disable
CPLD register clear or
preset delay
CPLD register clear or
preset pulse width
CPLD array delay
CPLD input pin/feedback
to CPLD combinatorial
output
CPLD input to CPLD
Output Enable
CPLD input to CPLD
Output Disable
CPLD register clear or
preset delay
CPLD register clear or
preset pulse width
CPLD array delay
Parameter
Parameter
Conditions
Conditions
macrocell
macrocell
Any
Any
Min
Min
18
10
Max
Max
35
38
38
35
20
20
21
21
21
11
Aloc
Aloc
+ 4
+ 4
+ 2
+ 2
PT
PT
DC and AC parameters
Turbo
Turbo
+ 10
+ 10
+ 10
+ 10
+ 10
+ 15
+ 15
+ 15
+ 15
+ 15
off
off
rate
rate
Slew
Slew
– 2
– 2
– 2
– 2
– 6
– 6
– 6
– 6
(1)
(1)
279/300
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns