MC68HC711K4CFU4

Manufacturer Part NumberMC68HC711K4CFU4
DescriptionIC MCU 24K 4MHZ EEPROM 80-QFP
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711K4CFU4 datasheets
 


Specifications of MC68HC711K4CFU4

Core ProcessorHC11Core Size8-Bit
Speed4MHzConnectivitySCI, SPI
PeripheralsPOR, PWM, WDTNumber Of I /o62
Program Memory Size24KB (24K x 8)Program Memory TypeOTP
Eeprom Size640 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case80-QFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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M68HC11K/D
M68HC11K Family
Technical Data
HCMOS
Microcontroller Unit

MC68HC711K4CFU4 Summary of contents

  • Page 1

    M68HC11K/D M68HC11K Family Technical Data HCMOS Microcontroller Unit ...

  • Page 2

    ... Freescale Semiconductor, Inc. blank For More Information On This Product, Go to: www.freescale.com ...

  • Page 3

    ... Freescale Semiconductor, Inc. MC68HC11K Family Technical Data Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...

  • Page 4

    ... Freescale Semiconductor, Inc. Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors The following revision history table summarizes changes contained in this document ...

  • Page 5

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family Section 1. General Description . . . . . . . . . . . . . . . . . . . . 25 Section 2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . 31 Section 3. Central Processor Unit (CPU Section 4. Operating Modes Section 5. Resets and Interrupts . . . . . . . . . . . . . . . . . . 105 Section 6. Parallel Input/Output . . . . . . . . . . . . . . . . . . . 135 Section 7. Serial Communications Section 8. Serial Peripheral Interface (SPI 167 Section 9. Timing System 181 Section 10 ...

  • Page 6

    ... Freescale Semiconductor, Inc. List of Sections Technical Data 6 List of Sections For More Information On This Product, Go to: www.freescale.com M68HC11K Family MOTOROLA ...

  • Page 7

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family 1.1 1.2 1.3 1.4 1.5 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 M68HC11K Family MOTOROLA For More Information On This Product, Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M68HC11K Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Structure ...

  • Page 8

    ... Freescale Semiconductor, Inc. Table of Contents 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 3.3.6.4 3.3.6.5 3.3.6.6 3.3.6.7 3.3.6.8 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.7 Technical Data 8 Section 3. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CPU Registers ...

  • Page 9

    ... Freescale Semiconductor, Inc. Section 4. Operating Modes and On-Chip Memory 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.7 4.7.1 4.7.2 4.8 4.8.1 4.8.1.1 4.8.1.2 4.8.1.3 4.8.2 4.8.2.1 4.8.2.2 4.8.2.3 4.8.2.4 4.8.3 4.8.4 M68HC11K Family ...

  • Page 10

    ... Freescale Semiconductor, Inc. Table of Contents 4.9 4.9.1 4.9.2 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.3.1 5.3.3.2 5.3.3.3 5.3.4 5.3.4.1 5.3.4.2 5.4 5.5 5.5.1 5.5.1.1 5.5.1.2 5.5.1.3 5.5.2 5.6 5.7 5.8 5.8.1 5.8.2 5.8.3 Technical Data 10 XOUT Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 System Configuration Register 102 System Configuration Options 2 Register ...

  • Page 11

    ... Freescale Semiconductor, Inc. 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 Section 7. Serial Communications Interface (SCI) 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 M68HC11K Family MOTOROLA For More Information On This Product, Section 6 ...

  • Page 12

    ... Freescale Semiconductor, Inc. Table of Contents 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 Technical Data 12 Section 8. Serial Peripheral Interface (SPI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Introduction ...

  • Page 13

    ... Freescale Semiconductor, Inc. 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.6.6 9.6.7 9.6.8 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.8 9.8.1 9.8.2 9.8.3 9.9 9.9.1 9.9.2 9.9.2.1 9.9.2.2 9.9.2.3 9.9.2.4 9.9.2.5 M68HC11K Family MOTOROLA For More Information On This Product, Input Capture (IC) ...

  • Page 14

    ... Freescale Semiconductor, Inc. Table of Contents 9.9.2.6 9.9.2.7 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.4.1 10.4.2 10.4.3 10.5 10.5.1 10.5.2 11.1 11.2 11.3 11.3.1 11.3.2 11.3.2.1 11.3.2.2 11.3.2.3 11.3.2.4 Technical Data 14 Pulse-Width Modulation Timer Periods Registers . . . . . . . . . . . . . . . . . . . . . . 218 Pulse-Width Modulation Timer Duty Cycle Registers ...

  • Page 15

    ... Freescale Semiconductor, Inc. 11.4 11.4.1 11.4.2 11.4.3 11.4.3.1 11.4.3.2 11.4.3.3 11.4.3.4 11.4.3.5 11.4.4 11.4.4.1 11.4.4.2 11.4.5 11.5 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . 265 12.11 Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 12.12 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . 269 12 ...

  • Page 16

    ... Freescale Semiconductor, Inc. Table of Contents 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 Technical Data 16 Section 13. Mechanical Data Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 84-Pin Plastic-Leaded Chip Carrier (Case 780 275 84-Pin J-Cerquad (Case 780A .276 80-Pin Quad Flat Pack (Case 841B 277 80-Pin Low-Profile Quad Flat Pack (Case 917A) ...

  • Page 17

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family Figure 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 Block Protect Register (BPROT 4-11 System Configuration Options Register (OPTION 4-12 Block Protect Register (BPROT) ...

  • Page 18

    ... Freescale Semiconductor, Inc. List of Figures Figure 4-13 System Configuration Register (CONFIG 101 4-14 System Configuration Register (CONFIG 102 4-15 System Configuration Options 2 Register (OPT2 .103 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 Interrupt Priority Resolution Within SCI System . . . . . . . . . . . 129 5-11 System Configuration Options Register (OPTION) ...

  • Page 19

    ... Freescale Semiconductor, Inc. Figure 6-17 Port Pullup Assignment Register (PPAR 147 6-18 System Configuration Register (CONFIG 147 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 SCI Status Register 2 (SCSR2 .164 7-11 SCI Data Register (SCDR 165 8-1 8-2 8-3 ...

  • Page 20

    ... Freescale Semiconductor, Inc. List of Figures Figure 9-13 Timer Output Compare 9-14 Timer Input Capture 4/Output 9-15 Timer Interrupt Flag 1 Register (TFLG1 199 9-16 Timer Interrupt Mask 1 Register (TMSK1 200 9-17 Timer Control Register 1 (TCTL1 200 9-18 Timer Compare Force Register (CFORC 201 9-19 Output Compare 1 Mask Register (OC1M) ...

  • Page 21

    ... Freescale Semiconductor, Inc. Figure 10-3 System Configuration Options Register (OPTION 227 10-4 Analog-to-Digital Control/Status Register (ADCTL 227 10-5 Analog-to-Digital Result Registers (ADR1–ADR4 229 10-6 Electrical Model of an A/D Input Pin (Sample Mode 230 11-1 Port G Assignment Register (PGAR 235 11-2 Memory Mapping Size Register (MMSIZ 235 11-3 Memory Mapping Window Base Register (MMWBR) ...

  • Page 22

    ... Freescale Semiconductor, Inc. List of Figures Figure 12-3 POR External Reset Timing Diagram . . . . . . . . . . . . . . . . . . .260 12-4 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 261 12-5 WAIT Recovery from Inerrupt Timing Diagram 262 12-6 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 12-7 Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 12-8 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 12-9 Expansion Bus Timing ...

  • Page 23

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family Table 1-1 2-1 2-2 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 XOUT Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 M68HC11K Family MOTOROLA For More Information On This Product, Title M68HC11K Family Devices ...

  • Page 24

    ... Freescale Semiconductor, Inc. List of Tables Table 7-1 7-2 8-1 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 10-1 A/D Converter Channel Selection 225 11-1 CPU Address and Address Expansion Signals . . . . . . . . . . . 233 11-2 Window Size Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 11-3 Memory Expansion Window Base Address . . . . . . . . . . . . . . 236 11-4 Chip Select Control Parameter Summary ...

  • Page 25

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family 1.1 Contents 1.2 1.3 1.4 1.5 1.2 Introduction The M68HC11K Family of high-performance microcontroller units (MCUs) offers a non-multiplexed expanded bus, high speed and low power consumption. The fully static design allows operation at frequencies from MHz. ...

  • Page 26

    ... Freescale Semiconductor, Inc. General Description 1.3 M68HC11K Family Members M68HC11K Family devices feature input/output (I/O) lines distributed among eight ports, A through H. The KS Family removes seven pins from port G and four pins from port H for a total of 51 I/O lines. The KSx versions feature a slow mode for the clocks to allow power conservation ...

  • Page 27

    ... Freescale Semiconductor, Inc. 1.4 Features M68HC11K Family features include: • • • • • • • • • • • M68HC11K Family MOTOROLA For More Information On This Product, 8-bit opcodes and data 16-bit addressing Two 8-bit accumulators, which can be concatenated to form one ...

  • Page 28

    ... Freescale Semiconductor, Inc. General Description • • • • • • • Technical Data 28 Enhanced synchronous serial peripheral interface (SPI) 8-channel, 8-bit, analog-to-digital (A/D) converter Computer operating properly (COP) watchdog system to guard against infinite loops and other system problems Real-time interrupt timer Power-saving modes: – ...

  • Page 29

    ... Freescale Semiconductor, Inc. 1.5 Structure Figure 1-1 Figure 1-2 MODA/ LIR RESET IRQ INTERRUPT (2) CONTROL LOGIC XIRQ/V PP PAI/OC1 PA7 PA6 OC2/OC1 PA5 OC3/OC1 OC4/OC1 PA4 IC4/OC5/OC1 PA3 PA2 IC1 IC2 PA1 IC3 PA0 24 KBYTES ROM/EPROM ADDRESS BUS DDRB PORT B Notes: 1. XOUT pin omitted on 80-pin QFP 2 ...

  • Page 30

    ... Freescale Semiconductor, Inc. General Description MODA/ LIR RESET IRQ INTERRUPT (2) LOGIC XIRQ/V PP PA7 PAI/OC1 OC2/OC1 PA6 PA5 OC3/OC1 OC4/OC1 PA4 IC4/OC5/OC1 PA3 PA2 IC1 PA1 IC2 PA0 IC3 MC68HC11KS2 32 KBYTES ROM/EPROM ADDRESS BUS DDRB PORT B Notes: 1. The configuration shown in this diagram is the MC68HC11KS2. ...

  • Page 31

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.2 Introduction The M68HC11K Family is available in a variety of packages, as shown in Table 1-1. M68HC11K Family two or more functions, as described in this section. Pin assignments for ...

  • Page 32

    ... Freescale Semiconductor, Inc. Pin Description PH0/PW1 12 PH1/PW2 13 PH2/PW3 14 PH3/PW4 15 PH4/CSIO 16 PH5/CSGP1 17 PH6/CSGP2 18 PH7/CSPROG 19 (1) TEST16 20 (2) XIRQ (1) 22 TEST15 (1) TEST14 25 PG7/R/W 26 PG6 27 PG5/XA18 28 PG4/XA17 29 PG3/XA16 30 PG2/XA15 31 PG1/XA14 32 Notes: 1. Pins 20, 22, and 25 are used only during factory testing and should not be connected to external circuitry. ...

  • Page 33

    ... Freescale Semiconductor, Inc. PD3/MOSI 1 PD4/SCK 2 PD5/SS 3 PA7/PAI/OC1 4 PA6/OC2/OC1 5 PA5/OC3/OC1 6 PA4/OC4/OC1 7 PA3/IC4/OC5/OC1 8 PA2/IC1 9 PA1/IC2 10 PA0/IC3 PB7/ADDR15 14 PB6/ADDR14 15 PB5/ADDR13 16 PB4/ADDR12 17 PB3/ADDR11 18 PB2/ADDR10 19 PB1/ADDR9 applies only to EPROM devices. PP Figure 2-2. Pin Assignments for M6811K 80-Pin QFP M68HC11K Family MOTOROLA For More Information On This Product, Pin Description Go to: www ...

  • Page 34

    ... Freescale Semiconductor, Inc. Pin Description PB7/ADDR15 10 PB6/ADDR14 11 PB5/ADDR13 12 PB4/ADDR12 13 PB3/ADDR11 14 PB2/ADDR10 15 PB1/ADDR9 16 PB0/ADDR8 17 PH0/PW1 18 PH1/PW2 19 PH2/PW3 20 PH3/PW4 21 XIRQ PG7/R/W 23 IRQ PE7/AN7 applies only to EPROM devices. PP Figure 2-3. Pin Assignments for M6811KS 68-Pin PLCC/J-Cerquad Technical Data 34 Pin Description For More Information On This Product, Go to: www ...

  • Page 35

    ... Freescale Semiconductor, Inc. PD0/RXD 1 PD1/TXD 2 PD2/MISO 3 PD3/MOSI 4 PD4/SCK 5 PD5/ PA7/PAI/OC1 14 PA6/OC2/OC1 15 PA5/OC3/OC1 16 PA4/OC4/OC1 17 PA3/IC4/OC5/OC1 18 PA2/IC1 19 PA1/IC2 20 PA0/IC3 * V applies only to EPROM devices. PP Figure 2-4. Pin Assignments for M6811KS 80-Pin LQFP M68HC11K Family MOTOROLA For More Information On This Product, Pin Description Go to: www.freescale.com ...

  • Page 36

    ... Freescale Semiconductor, Inc. Pin Description 2.3 Power Supply (V DD The MCU operates from a single 5-volt (nominal) power supply. V the positive power input and V pairs of pins on the K series devices and two sets on the KS devices. All devices contain a separate pair of power inputs, AV analog-to-digital (A/D) converter, so that the A/D circuitry can be bypassed independently ...

  • Page 37

    ... Freescale Semiconductor, Inc. MANUAL RESET SWITCH 4.7 k OPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCH It is important to protect the MCU against corruption of RAM and EEPROM during power transitions. This can be done with a low-voltage interrupt (LVI) circuit which holds the RESET pin low when V below the minimum operating level ...

  • Page 38

    ... Freescale Semiconductor, Inc. Pin Description 2.6 XOUT The XOUT pin provides a buffered clock signal if enabled to synchronize external devices with the MCU. See NOTE: This signal is not present on the 80-pin M68HC(7)11K device QFP package. 2.7 E-Clock Output (E) The internally generated instruction cycle clock clock, is available on the E pin as a timing reference ...

  • Page 39

    ... Freescale Semiconductor, Inc. Mode Selection, Instruction Cycle Reference, and Standby Power (MODA/LIR and MODB/VSTBY) required for wire-OR configuration. Software can change the triggering to edge sensitive. XIRQ interrupts can be non-maskable after reset initialization. Out of reset, the X bit in the CCR is set, masking XIRQ interrupts. Once software clears the X bit, it cannot be reset, and the XIRQ interrupts become non-maskable ...

  • Page 40

    ... Freescale Semiconductor, Inc. Pin Description In single-chip and bootstrap modes, the MODA pin typically is grounded and has no function after reset. In expanded and special test modes, MODA is normally connected to V and functions as the load instruction register (LIR) pin after reset. The open-drain, active-low LIR output drives low during the first E-clock cycle of each instruction (opcode fetch), providing a useful signal for system debugging ...

  • Page 41

    ... Freescale Semiconductor, Inc. The MODB pin is grounded to select special modes, and has no function after reset. To select the normal operating modes (single-chip and expanded) the MODB pin is pulled to a logic high level. Connecting MODB to a voltage source other than V battery backup input, V threshold (about 0 ...

  • Page 42

    ... Freescale Semiconductor, Inc. Pin Description 51 I/O lines. All ports are fully bidirectional except port E, which is input only. Each port can serve as either general-purpose I part of the microcontroller’s specialized functions, depending on the operating mode or peripheral functions selected. The functions of ports B, C, and F and port G bit 7 depend on the operating mode ...

  • Page 43

    ... Freescale Semiconductor, Inc. M68HC11K Family MOTOROLA For More Information On This Product, Table 2-2. Port Signal Summary Single-Chip and Port/Bit Bootstrap Modes PA0 PA0/IC3 PA1 PA1/IC2 PA2 PA2/IC1 PA3 PA3/OC5/IC4/and-or OC1 PA4 PA4/OC4/and-or OC1 PA5 PA5/OC3/and-or OC1 PA6 PA6/OC2/and-or OC1 PA7 PA7/PAI/and-or OC1 ...

  • Page 44

    ... Freescale Semiconductor, Inc. Pin Description Technical Data 44 Pin Description For More Information On This Product, Go to: www.freescale.com M68HC11K Family MOTOROLA ...

  • Page 45

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family 3.1 Contents 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 3.3.6.4 3.3.6.5 3.3.6.6 3.3.6.7 3.3.6.8 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.7 M68HC11K Family MOTOROLA For More Information On This Product, Section 3 ...

  • Page 46

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.2 Introduction This section presents information on M68HC11 central processor unit (CPU) architecture, data types, addressing modes, the instruction set, and special operations, such as subroutine calls and interrupts. The CPU employs memory-mapped input/output (I/O). There are no special instructions for I/O ...

  • Page 47

    ... Freescale Semiconductor, Inc. 3.3.1 Accumulators A, B, and D (ACCA, ACCB, and ACCD) Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. Some instructions treat these two accumulators as a single double-byte (16-bit) accumulator called accumulator D. Most operations can use either accumulator with these exceptions: • ...

  • Page 48

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.3.4 Stack Pointer (SP) The stack pointer holds the 16-bit address of the next free location in the M68HC11 CPU’s automatic program stack. This stack is a data structure that grows downward from high memory to low memory. The stack can be located anywhere in the address space and can be any size up to the amount of memory available in the system ...

  • Page 49

    ... Freescale Semiconductor, Inc. JSR, JUMP TO SUBROUTINE MAIN PROGRAM PC $9D = JSR dd DIRECT NEXT MAIN INSTR. RTN MAIN PROGRAM PC $AD = JSR ff INDEXED, X NEXT MAIN INSTR. RTN MAIN PROGRAM PC $18 = PRE INDEXED, Y $AD = JSR ff RTN NEXT MAIN INSTR. MAIN PROGRAM PC $BD = PRE hh INDEXED RTN NEXT MAIN INSTR ...

  • Page 50

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.3.5 Program Counter (PC) The 16-bit program counter contains the address of the next instruction to be executed. Its initial value after reset is fetched from one of six possible vectors, depending on operating mode and the cause of reset, as described in 3 ...

  • Page 51

    ... Freescale Semiconductor, Inc. an internal implied subtraction and the condition codes, including Z, reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags. 3.3.6.4 Negative (N) The N bit is set if the result of an arithmetic, logic, or data manipulation operation is negative, meaning that the most significant bit (MSB) of the result ...

  • Page 52

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.3.6.7 Non-Maskable Interrupt (X) Setting the XIRQ mask (X) bit disables non-maskable interrupts from the XIRQ pin. Every reset sets the X bit by default and only a software instruction can clear it. When the processor recognizes a non-maskable interrupt, it stacks the registers, sets the X and I bits, and then fetches the interrupt vector ...

  • Page 53

    ... Freescale Semiconductor, Inc. there are no special requirements for alignment of instructions or operands. 3.5 Opcodes and Operands The M68HC11 Family of microcontrollers uses 8-bit opcodes. Every instruction requires a unique opcode for each of its addressing modes. The resulting number of opcodes exceeds the 256 available in an 8-bit binary number ...

  • Page 54

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.6.1 Immediate In the immediate addressing mode, the byte(s) immediately following the opcode contain the arguments. The number of bytes following the opcode matches the size of the register or memory location being used. Immediate instructions can be two, three, or (if a prebyte is required) four bytes ...

  • Page 55

    ... Freescale Semiconductor, Inc. 3.6.5 Inherent In the inherent addressing mode, the opcode contains all required information. The operands (if any) are registers memory access is required. This mode includes: • • These instructions are one or two bytes. 3.6.6 Relative Only branch instructions use the relative addressing mode. If the branch ...

  • Page 56

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-1. Instruction Set (Sheet Mnemonic Operation Description ABA Add Accumulators ABX Add ( ABY Add ( ADCA (opr) Add with Carry ADCB (opr) Add with Carry ADDA (opr) Add Memory ADDB (opr) Add Memory ADDD (opr) ...

  • Page 57

    ... Freescale Semiconductor, Inc. Table 3-1. Instruction Set (Sheet Mnemonic Operation Description BEQ (rel) Branch if = Zero ? BGE (rel) Branch if Zero ? BGT (rel) Branch if > Zero ? BHI (rel) Branch Higher BHS (rel) Branch Higher or Same BITA (opr) Bit(s) Test A A • M with Memory ...

  • Page 58

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-1. Instruction Set (Sheet Mnemonic Operation Description COM (opr) Ones $FF – M Complement Memory Byte COMA Ones $FF – A Complement A COMB Ones $FF – B Complement B CPD (opr) Compare – Memory 16-Bit CPX (opr) Compare – Memory 16-Bit ...

  • Page 59

    ... Freescale Semiconductor, Inc. Table 3-1. Instruction Set (Sheet Mnemonic Operation Description INS Increment Stack Pointer INX Increment Index Register X INY Increment Index Register Y JMP (opr) Jump See Figure 3-2 JSR (opr) Jump to See Figure 3-2 Subroutine LDAA (opr) Load M A Accumulator ...

  • Page 60

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-1. Instruction Set (Sheet Mnemonic Operation Description LSRD Logical Shift Right Double MUL Multiply NEG (opr) Two’s 0 – M Complement Memory Byte NEGA Two’s 0 – A Complement A NEGB Two’s 0 – B Complement B NOP ...

  • Page 61

    ... Freescale Semiconductor, Inc. Table 3-1. Instruction Set (Sheet Mnemonic Operation Description SBA Subtract B from A – SBCA (opr) Subtract with A – M – C Carry from A SBCB (opr) Subtract with B – M – C Carry from B SEC Set Carry 1 C SEI Set Interrupt 1 I Mask SEV ...

  • Page 62

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-1. Instruction Set (Sheet Mnemonic Operation Description TPA Transfer CC CCR Register to A TST (opr) Test for Zero or M – 0 Minus TSTA Test A for Zero A – Minus TSTB Test B for Zero B – Minus TSX ...

  • Page 63

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family Section 4. Operating Modes and On-Chip Memory 4.1 Contents 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.7 4.7.1 4.7.2 4.8 4.8.1 4.8.1.1 4.8.1.2 4.8.1.3 4.8.2 4.8.2.1 4.8.2.2 4 ...

  • Page 64

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 4.2 Introduction This section presents the elements involved in configuring the M68HC11K/KS Family microcontrollers (MCUs), including: • • • • • 4.3 Control Registers The heart of the M68HC11 Family of MCUs is a special register block which controls the peripheral functions ...

  • Page 65

    ... Freescale Semiconductor, Inc. NOTE: Throughout this manual, the registers are discussed by function. In the event that not all bits in a register are referenced, the bits that are not discussed are shaded. Addr. Register Name Read: Port A Data Register $0000 (PORTA) Write: See page 138. ...

  • Page 66

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Addr. Register Name Read: Port E Data Register $000A (PORTE) Write: See page 143. Reset: Read: Timer Compare Force $000B Register (CFORC) Write: See page 201. Reset: Read: Output Compare 1 $000C Mask Register (OC1M) Write: See page 202 ...

  • Page 67

    ... Freescale Semiconductor, Inc. Addr. Register Name Read: Timer Input Capture 3 $0015 Register Low (TIC3L) Write: See page 192. Reset: Timer Output Read: Compare 1 High Write: $0016 Register (TOC1H) Reset: See page 197. Timer Output Read: Compare 1 Low Write: $0017 Register (TOC1L) Reset: See page 197 ...

  • Page 68

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Addr. Register Name Timer Input Capture 4/ Read: Output Compare 5 Reg. Write: $001E High (TI4H/O5H) Reset: See page 199. Timer Input Capture 4/ Read: Output Compare 5 Reg. Write: $001F Low (TI4L/O5L) Reset: See page 199. ...

  • Page 69

    ... Freescale Semiconductor, Inc. Addr. Register Name Serial Peripheral Read: Control Register Write: $0028 (SPCR) Reset: See page 174. Read: Serial Peripheral Status $0029 Register (SPSR) Write: See page 176. Reset: Read: Serial Peripheral Data $002A Register (SPDR) Write: See page 177. ...

  • Page 70

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Addr. Register Name Analog-to-Digital Read: Results Register 2 Write: $0032 (ADR2) Reset: See page 229. Analog-to-Digital Read: Results Register 3 Write: $0033 (ADR3) Reset: See page 229. Analog-to-Digital Read: Results Register 4 Write: $0034 (ADR4) Reset: See page 229 ...

  • Page 71

    ... Freescale Semiconductor, Inc. Addr. Register Name Arm/Reset COP Timer Read: Circuitry Register Write: $003A (COPRST) Reset: See page 110. EEPROM Programming Read: Control Register Write: $003B (PPROG) Reset: See page 91. Highest Priority I-Bit Read: Interrupt and Misc. Write: $003C Register (HPRIO) ...

  • Page 72

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Addr. Register Name Memory Mapping Read: Window 1 Control Write: $0058 (1) Register (MM1CR) Reset: See page 237. Memory Mapping Read: Window 2 Control Write: $0059 (1) Register (MM2CR) Reset: See page 237. Chip Select Clock Read: ...

  • Page 73

    ... Freescale Semiconductor, Inc. Addr. Register Name Pulse Width Modulation Read: Timer Prescaler Write: $0062 Register (PWSCAL) Reset: See page 215. Pulse Width Modulation Read: Timer Enable Register Write: $0063 (PWEN) Reset: See page 216. Pulse Width Modulation Read: Timer Counter 1 Write: ...

  • Page 74

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Addr. Register Name Pulse Width Modulation Read: Timer Duty Cycle 1 Write: $006C Register (PWDTY1) Reset: See page 219. Pulse Width Modulation Read: Timer Duty Cycle 2 Write: $006D Register (PWDTY2) Reset: See page 219. ...

  • Page 75

    ... Freescale Semiconductor, Inc. Addr. Register Name Read: SCI Data Register $0077 (SCDR) Write: See page 165. Reset: $0078 Reserved to $007B Reserved Read: Port H Data Register $007C (PORTH) Write: See page 146. Reset: Read: Port H Data Direction $007D Register (DDRH) Write: See page 146. ...

  • Page 76

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 4.4 System Initialization Registers and bits that control initialization and the basic operation of the MCU are protected against writes except under special circumstances. Table 4-1 must be written within the first 64 cycles after reset. ...

  • Page 77

    ... Freescale Semiconductor, Inc. 4.5 Operating Modes The two normal modes of operation in the M68HC11K Family are: • • The two special modes of operation are: • • The logic levels applied at reset to input pins MODA and MODB determine the operating mode. See 4.5.1 Single-Chip Mode In single-chip mode, the MCU functions as a self-contained microcontroller ...

  • Page 78

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Port B provides the high-order address byte (Addr[15:8]), port F the low-order address byte (Addr[7:0]), port C the data bus (Data[7:0]), and port G pin 7 the read/write line (R/W) which controls direction of data flow. Additionally, the E clock output can be used to synchronize external decoders for enable signals ...

  • Page 79

    ... Freescale Semiconductor, Inc. Synchronization For a detailed description of bootstrap mode, refer to the Motorola application note entitled MC68HC11 Bootstrap Mode, document order number AN1060/D. 4.5.4 Special Test Mode Special test mode, a variation of the expanded mode, is used primarily during Motorola’s internal production testing. However, for those devices ...

  • Page 80

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Table 4-3 latched. The HPRIO register is illustrated in MODB Address: $003C Read: Write: Reset: 1. The values of the RBOOT, SMOD, and MDA bits at reset depend on the mode during initialization. RBOOT — Read Bootstrap ROM Bit In special modes, this bit enables the bootloader ROM In normal modes this bit is clear and cannot be written ...

  • Page 81

    ... Freescale Semiconductor, Inc. mode from special to normal, but not vice versa. To switch from a special mode to a normal mode, write to the access-limited registers (see MDA — Mode Select A Bit The mode select A bit reflects the status of the MODA input pin at the rising edge of RESET. Software can change the MDA bit only while the SMOD bit is set, effectively switching the operating mode between special bootstrap and special test modes ...

  • Page 82

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory $0000 $0380 EXTERNAL $0D80 $1000 EXTERNAL $A000 $FFC0 $FFFF SINGLE EXPANDED BOOTSTRAP CHIP Note 1.EPROM can be enabled in special test mode by setting the ROMON bit in the CONFIG register after reset. Figure 4-3. M68HC11K4 Family Memory Map ...

  • Page 83

    ... Freescale Semiconductor, Inc. $0000 $0480 EXTERNAL $0D80 $1000 EXTERNAL $8000 $FFC0 $FFFF SINGLE- EXPANDED BOOTSTRAP CHIP Note: 1.EPROM can be enabled in special test mode by setting the ROMON bit in the CONFIG register after reset. Figure 4-4. M68HC11KS2 Family Memory Map Table 4-4 Family devices. ...

  • Page 84

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 4.6.1 Control Registers and RAM Out of reset, the 128-byte register block is mapped to $0000 and the 768-byte RAM (1 Kbyte on the [7]11KS2) is mapped to $0080. Both the register block and the RAM can be placed at any other 4-Kbyte boundary ($x000 and $x080, respectively) by writing the appropriate value to the INIT register ...

  • Page 85

    ... Freescale Semiconductor, Inc. RAM[3:0] 1. RAM[3:0] = REG[3:0]: On the [7]11KS2, RAM address range is $x080–$x47F. 2. RAM[3:0] 3. Default locations out of reset M68HC11K Family MOTOROLA For More Information On This Product, Table 4-5. RAM Mapping (1) Address 0000 $0080–$037F 0001 $1080–$137F 0010 $2080– ...

  • Page 86

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Since the direct addressing mode accesses RAM more quickly and efficiently than other addressing modes, many applications will find the default locations of registers and on-board RAM at the bottom of memory to be the most advantageous. ...

  • Page 87

    ... Freescale Semiconductor, Inc. 4.6.2 ROM or EPROM The presence and location of the 24-Kbyte (EP)ROM on the [7]11K4 is determined by two bits in the system configuration register (CONFIG). The CONFIG register is a special EEPROM register (see (EP)ROM is present in the memory map when the ROMON bit is set and removed from the memory map when the bit is cleared. The default location of this memory is $A000– ...

  • Page 88

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Address: $003F Read: Write: Reset: NOTE: CONFIG is writable once in normal modes and writable at any time in special modes. ROMAD — ROM Address Mapping Control Bit Set out of reset in single-chip mode ROMON — ROM/PROM Enable Bit Set by reset in single-chip mode ...

  • Page 89

    ... Freescale Semiconductor, Inc. Address: $0037 Read: Write: Reset: NOTE: INIT2 is writable once in normal modes and writable at any time in special modes. EE[3:0] — EEPROM Map Position Bits These four bits determine the most-significant hexadecimal digit in the address range of the EEPROM, as shown in M68HC11K Family ...

  • Page 90

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 4.6.4 Bootloader ROM The bootloader program occupies 512 bytes of bootstrap ROM at addresses $BE00–$BFFF active only in special modes when the RBOOT bit in the HPRIO register is set. 4.7 EPROM/OTPROM (M68HC711K4 and M68HC711KS2) The M68HC711K4 devices include 24 Kbytes of on-chip EPROM (OTPROM in non-windowed packages) ...

  • Page 91

    ... Freescale Semiconductor, Inc. registers to default values, then receives data from an external host and programs it into the EPROM. The value in the X index register determines programming delay time. The value in the Y index register is a pointer to the first address in EPROM to be programmed. The default starting address is $8000 for the M68HC11KS2 ...

  • Page 92

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory ELAT — EPROM Latch Control Bit Setting ELAT latches the address and data of writes to the EPROM. The EPROM cannot be read. ELAT can be read at any time. ELAT can be written any time except when PGM = 1, which disables writes to ELAT. EXCOL — ...

  • Page 93

    ... Freescale Semiconductor, Inc. This procedure programs one byte into EPROM. On entry, accumulator A contains the byte of data to be programmed and X contains the target EPROM address. EPROG LDAB 4.8 EEPROM and the CONFIG Register The 640-byte on-board EEPROM is enabled by the EEON bit in the ...

  • Page 94

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory both EELAT and EPGM during the same write operation results in neither bit being set. 4.8.1 EEPROM Registers This section describes the EEPROM registers: • • • The EEPROM programming control register (PPROG) controls programming and erasing ...

  • Page 95

    ... Freescale Semiconductor, Inc. LVPI — Low-Voltage Programming Inhibit Bit LVPI is a read-only bit which always reads as 0. The functionality of this status bit was changed from early versions of the M68HC11K Family. The low-voltage programming inhibit function is disabled on all recent devices. BYTE — Byte/Other EEPROM Erase Mode Bit ROW — ...

  • Page 96

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 4.8.1.2 Block Protect Register This register prevents inadvertent writes to both the CONFIG register and EEPROM. The active bits in this register are initialized to 1 out of reset and can be cleared only during the first 64 E-clock cycles after reset in the normal modes ...

  • Page 97

    ... Freescale Semiconductor, Inc. 4.8.1.3 System Configuration Options Register Address: $0039 Read: Write: Reset: 1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes. Figure 4-11. System Configuration Options Register (OPTION) CSEL — Clock Select Bit Selects the built-in RC clock source for on-chip EEPROM and A/D charge pumps ...

  • Page 98

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory The procedures for both writing and erasing involve these five steps: 1. Set the EELAT bit in PPROG. If erasing, also set the ERASE bit 2. Write data to the appropriate EEPROM address. If erasing, any 3. Set the EEPGM bit in PPROG, keeping EELAT set. If erasing, 4 ...

  • Page 99

    ... Freescale Semiconductor, Inc. 4.8.2.2 EEPROM Bulk Erase BULKE 4.8.2.3 EEPROM Row Erase ROWE 4.8.2.4 EEPROM Byte Erase BYTEE M68HC11K Family MOTOROLA For More Information On This Product, LDAB #$06 STAB $003B Set EELAT and ERASE. STAA $0,X Store any data to any EEPROM address ...

  • Page 100

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 4.8.3 CONFIG Register Programming The CONFIG register is implemented with EEPROM cells, so EEPROM procedures are required to change it. CONFIG can be programmed or erased (including byte erase) while the MCU is operating in any mode, provided that PTCON in BPROT is clear. ...

  • Page 101

    ... Freescale Semiconductor, Inc. Address: $003F Read: Write: Reset: NOTE: CONFIG is writable once in normal modes and writable at any time in special modes. NOSEC — RAM and EPROM Security Disabled Bit M68HC11K Family devices are normally manufactured with NOSEC set and the security option unavailable. However, on special request, a mask option is selected during fabrication that enables the security mode ...

  • Page 102

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 4.9 XOUT Pin Control The XOUT pin provides a buffered XTAL signal to synchronize external devices with the MCU enabled by the CLKX bit in the system configuration (CONFIG) register. The frequency of XOUT can be divided by one-of-four divisors selected by the XDV[1:0] bits in the system configuration options 2 (OPT2) register ...

  • Page 103

    ... Freescale Semiconductor, Inc. 4.9.2 System Configuration Options 2 Register Address: $0038 Read: Write: Reset: Figure 4-15. System Configuration Options 2 Register (OPT2) XDV[1:0] — XOUT Clock Divide Select Bits These two bits select the divisor for the XOUT clock frequency, as shown in (XOUT = XTAL). It takes a maximum of 16 cycles after writing these bits for XOUT to stabilize ...

  • Page 104

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Technical Data 104 Operating Modes and On-Chip Memory For More Information On This Product, Go to: www.freescale.com M68HC11K Family MOTOROLA ...

  • Page 105

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family 5.1 Contents 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.3.1 5.3.3.2 5.3.3.3 5.3.4 5.3.4.1 5.3.4.2 5.4 5.5 5.5.1 5.5.1.1 5.5.1.2 5.5.1.3 5.5.2 5.6 5.7 5.8 5.8.1 5.8.2 5.8.3 M68HC11K Family MOTOROLA For More Information On This Product, Section 5 ...

  • Page 106

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.2 Introduction When a reset or interrupt occurs, the microcontroller (MCU) retrieves the starting address of a program or interrupt routine from a vector table in memory and loads it in the program counter. A reset immediately stops execution of the current instruction and reinitializes the control registers. ...

  • Page 107

    ... Freescale Semiconductor, Inc. 5.3.1 Power-On Reset (POR) A positive transition on V power-up conditions. POR cannot be used to detect drops in power supply voltages. The CPU delays 4064 internal clock cycles after the oscillator becomes active to allow the clock generator to stabilize, then checks the RESET pin. If RESET is at logical 0, the CPU remains in the reset condition until the RESET pin goes to logical 1 ...

  • Page 108

    ... Freescale Semiconductor, Inc. Resets and Interrupts Three registers are involved in COP operation: • • • NOTE: Throughout this manual, the registers are discussed by function. In the event that not all bits in a register are referenced, the bits that are not discussed are shaded. ...

  • Page 109

    ... Freescale Semiconductor, Inc. 5.3.3.2 System Configuration Options Register Two bits in the OPTION register select one of four values for the COP timer. Address: $0039 Read: Write: Reset: Figure 5-2. System Configuration Options Register (OPTION) CR[1:0] — COP Timer Rate Select Bits The MCU derives the counter for the COP timer by dividing the ...

  • Page 110

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.3.3.3 Arm/Reset COP Timer Circuitry Register Address: $003A Read: Write: Reset: Figure 5-3. Arm/Reset COP Timer Circuitry Register (COPRST) To prevent a COP reset, this sequence must be completed: 1. Write $55 to COPRST to arm the COP timer clearing mechanism. ...

  • Page 111

    ... Freescale Semiconductor, Inc. 5.3.4.1 System Configuration Options Register The clock monitor function is enabled or disabled by the CME control bit in the OPTION register (see overrides CME and enables the clock monitor until the next reset. Address: $0030 Read: Write: Reset: Figure 5-4. System Configuration Options Register (OPTION) ...

  • Page 112

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.3.4.2 System Configuration Options Register 2 Address: $0038 Read: Write: Reset: 1. Not available on M68HC11K devices Figure 5-5. System Configuration Options Register 2 (OPT2) LIRDV — LIR Driven Bit This bit allows power savings in expanded modes by turning off the LIR output (it has no meaning in single-chip or bootstrap modes) ...

  • Page 113

    ... Freescale Semiconductor, Inc. NOTE: STRCH is cleared on reset; therefore, a program cannot execute out of reset in a slow external ROM. To use the STRCH feature, ROMON must be set on reset so that the device starts with internal ROM included in the memory map. STRCH should then be set. STRCH has no effect in single-chip and bootstrap modes. ...

  • Page 114

    ... Freescale Semiconductor, Inc. Resets and Interrupts LSBF — Least Significant Bit (LSB) First Enable Bit For detailed information, refer to Interface SPR2 — SPI Clock Rate Selected Bit This bit adds a divide-by-four to the SPI clock chain. For detailed information, refer to XDV[1:0] — XOUT Clock Divide Select Bits These bits control the frequency of the clock driven out of the XOUT pin, if enabled by the CLKX bit on the CONFIG register ...

  • Page 115

    ... Freescale Semiconductor, Inc. 5.4 Effects of Reset When the MCU recognizes a reset condition, it forces the CPU registers and control bits to established initial states. These in turn force the on-chip peripheral systems to known startup states, as described here. • • • M68HC11K Family MOTOROLA For More Information On This Product, Central processor unit (CPU) – ...

  • Page 116

    ... Freescale Semiconductor, Inc. Resets and Interrupts • • • • Technical Data 116 – All nine timer interrupts are disabled because their mask bits have been cleared. – The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5; however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not control the PA3 pin ...

  • Page 117

    ... Freescale Semiconductor, Inc. • • • 5.5 Interrupts The MCU has 18 interrupt vectors that support 22 interrupt sources. The 19 maskable interrupts are generated by on-chip peripheral systems. They are recognized when the I bit in the CCR is clear. The three non-maskable interrupt sources are illegal opcode trap, software interrupt, and XIRQ pin ...

  • Page 118

    ... Freescale Semiconductor, Inc. Resets and Interrupts Table 5-5. Interrupt and Reset Vector Assignments Vector Address FFC0, C1 — FFD4, D5 FFD6, D7 FFD8, D9 FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB FFEC, ED FFEE, EF FFF0, F1 FFF2, F3 FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF Technical Data ...

  • Page 119

    ... Freescale Semiconductor, Inc. Many interrupt sources set associated flag bits when interrupts occur. These flags are usually cleared during the course of normal interrupt service. For example, the normal response to an RDRF interrupt request in the SCI is to read the SCI status register to check for receive errors, then read the received data from the SCI data register ...

  • Page 120

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.5.1 Non-Maskable Interrupts Non-maskable interrupts can interrupt CPU operations at any time. The most common use for such an interrupt is for serious system problems, such as program runaway or power failure. The three sources of non-maskable interrupt are: • • ...

  • Page 121

    ... Freescale Semiconductor, Inc. execution of the illegal opcode, which can lead to stack overflow, the service routine should reinitialize the stack pointer. 5.5.1.3 Software Interrupt (SWI) SWI cannot be masked by virtue of the fact that software instruction not inhibited by the global mask bits in the CCR. ...

  • Page 122

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.6 Reset and Interrupt Priority A hardware priority scheme determines which reset or interrupt is serviced first when simultaneous requests occur. The six highest-priority interrupt sources are not maskable. The priority arrangement for these sources is: 1. POR or RESET pin 2 ...

  • Page 123

    ... Freescale Semiconductor, Inc. Any single maskable interrupt can be given priority over other maskable interrupts by writing the appropriate value to the PSEL bits in the HPRIO register (see still subject to global masking by the I bit in the CCR or by any associated local bits. Interrupt vectors are not affected by priority assignment. ...

  • Page 124

    ... Freescale Semiconductor, Inc. Resets and Interrupts Technical Data 124 Table 5-7. Highest Priority Interrupt Selection PSELx Reserved (default to IRQ Reserved (default to IRQ Reserved (default to IRQ IRQ Real-time interrupt Timer input capture Timer input capture Timer input capture Timer output compare Timer output compare 2 ...

  • Page 125

    ... Freescale Semiconductor, Inc. HIGHEST PRIORITY POWER-ON RESET (POR) DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) Figure 5-8. Processing Flow Out of Reset (Sheet M68HC11K Family MOTOROLA For More Information On This Product, EXTERNAL RESET CLOCK MONITOR FAIL (WITH CME = 1) ...

  • Page 126

    ... Freescale Semiconductor, Inc. Resets and Interrupts STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF8, $FFF9 STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF6, $FFF7 Figure 5-8. Processing Flow Out of Reset (Sheet Technical Data 126 2A Y BIT I IN ...

  • Page 127

    ... Freescale Semiconductor, Inc. BEGIN X BIT IN CCR SET ? NO HIGHEST PRIORITY INTERRUPT ? NO IRQ ? NO RTII = IC1I = IC2I = IC3I = OC1I = Figure 5-9. Interrupt Priority Resolution (Sheet M68HC11K Family MOTOROLA For More Information On This Product, YES YES XIRQ PIN SET X BIT IN CCR LOW ? FETCH VECTOR $FFF4, FFF5 ...

  • Page 128

    ... Freescale Semiconductor, Inc. Resets and Interrupts 2A Y OC2I = OC3I = OC4I = OC5I = TOI = PAOVI = PAII = SPIE = SCI INTERRUPT? N Figure 5-9. Interrupt Priority Resolution (Sheet Technical Data 128 Y FLAG OC2F = FLAG OC3F = FLAG OC4F = FLAG OC5F = FLAG TOF = FLAG PAOVF = FLAG PAIF = 1? N FLAGS ...

  • Page 129

    ... Freescale Semiconductor, Inc. BEGIN FLAG Y RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 5-10. Interrupt Priority Resolution Within SCI System 5.8 Low-Power Operation The MCU contains two software instructions, WAIT and STOP, to reduce power consumption when processing is not required. Both instructions suspend operation until a reset or interrupt occurs while retaining register and RAM contents ...

  • Page 130

    ... Freescale Semiconductor, Inc. Resets and Interrupts 5.8.1 Wait Mode The WAI opcode places the MCU in the wait condition, during which the CPU registers are stacked and CPU processing is suspended until a qualified interrupt is detected. The interrupt can be an external IRQ, an XIRQ, or any of the internally generated interrupts, such as the timer or serial interrupts ...

  • Page 131

    ... Freescale Semiconductor, Inc. to restart the system, a normal reset sequence results and all pins and registers are reinitialized. To use the IRQ pin as a means of recovering from STOP, the I bit in the CCR must be clear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from STOP regardless of the state of the X bit in the CCR, although the state of this bit does affect the recovery sequence ...

  • Page 132

    ... Freescale Semiconductor, Inc. Resets and Interrupts DLY — Enable Oscillator Startup Delay Bit This bit is set during reset and can be written only once during the first 64 E-clock cycles after reset in normal modes. This bit can be used to inhibit the oscillator startup delay after reset when using an external clock source ...

  • Page 133

    ... Freescale Semiconductor, Inc. NOTE: The slow mode function should not be enabled while using the A/D converter or during an erase/program operation of the EEPROM, unless the internal RC oscillator is turned on. The clock monitor function should not be used if the resultant E clock will be slower than 200 kHz. ...

  • Page 134

    ... Freescale Semiconductor, Inc. Resets and Interrupts Technical Data 134 Resets and Interrupts For More Information On This Product, Go to: www.freescale.com M68HC11K Family MOTOROLA ...

  • Page 135

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family 6.1 Contents 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 M68HC11K Family MOTOROLA For More Information On This Product, Section 6. Parallel Input/Output Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Port 138 Port 139 Port 140 Port 142 Port E ...

  • Page 136

    ... Freescale Semiconductor, Inc. Parallel Input/Output 6.2 Introduction The M68HC11K series MCUs contain eight input/output (I/O) ports, A through H. All ports can provide general-purpose I/O (GPIO) as well as their specialized functions, as explained in summarized in Port Port A Port B Port C Port D Port E Port F Port G Port devices do not contain port G[6:0], so they have only one bidirectional pin on this port. ...

  • Page 137

    ... Freescale Semiconductor, Inc. Ports and H contain on-chip pullup devices which are enabled by the port pullup assignment register (PPAR) described in Pullup At reset, the ports are configured as high-impedance GPIO inputs (except for ports and port G pin 7 in expanded modes). The contents of the data latches is undefined. If any of the bidirectional pins are changed to outputs before writing to the associated data registers, the undefined contents will be driven on the pins ...

  • Page 138

    ... Freescale Semiconductor, Inc. Parallel Input/Output 6.3 Port A Port A provides the I/O lines for the timer functions and pulse accumulator. The eight port A bits (PA[7:0]) are configured as high-impedance general-purpose inputs out of reset. Writes to DDRA can change any of the bits to outputs. Writes to timer registers enable ...

  • Page 139

    ... Freescale Semiconductor, Inc. 6.4 Port B The state of port B (PB[7:0]) at reset is mode dependent. In single-chip or bootstrap modes, port B pins are high-impedance inputs with selectable internal pullup resistors (see Resistors). Writes to DDRB can change any of the bits to outputs. In expanded or test modes, port B pins provide the high-order address lines ADDR[15:8] for external memory devices ...

  • Page 140

    ... Freescale Semiconductor, Inc. Parallel Input/Output 6.5 Port C The state of port C at reset is mode dependent. In single-chip or bootstrap modes, port C pins (PC[7:0]) are high-impedance inputs. Writes to DDRC can change any of the bits to outputs. In expanded or test modes, port C pins provide the data lines (DATA[7:0]) for external memory devices. The MCU’ ...

  • Page 141

    ... Freescale Semiconductor, Inc. Address: $0007 Read: Write: Reset: Figure 6-6. Port C Data Direction Register (DDRC) DDC[7:0] — Data Direction for Port C Bits Address: $0038 Read: Write: Reset: Figure 6-7. System Configuration Options 2 Register (OPT2) CWOM — Port C Wired-OR Mode Bit IRVNE — Internal Read Visibility/Not E Bit In expanded modes, setting this bit drives MCU’ ...

  • Page 142

    ... Freescale Semiconductor, Inc. Parallel Input/Output 6.6 Port D The six port D bits, PD[5:0] function as the serial communication interface (see the serial peripheral interface (see Interface high-impedance general-purpose inputs out of reset; DDRD can be used to change any of the pins to outputs. Address: $0008 Read: Write: ...

  • Page 143

    ... Freescale Semiconductor, Inc. 6.7 Port E Port E, PE[7:0], is the only port that functions as input only, and its pins are configured as high-impedance inputs out of reset. It also serves as the analog input for the analog-to-digital converter when this function is enabled by software (see Converter). NOTE: PORT E should not be read during the sample portion of an A/D conversion ...

  • Page 144

    ... Freescale Semiconductor, Inc. Parallel Input/Output 6.8 Port F The state of port F (PF[7:0]) at reset is mode dependent. In single-chip or bootstrap modes, port F pins are high-impedance inputs with selectable internal pullup resistors (see Resistors). Writes to DDRF can change any of the bits to outputs. In expanded or test modes, port F pins provide low-order address lines, ADDR[7:0], for external memory devices ...

  • Page 145

    ... Freescale Semiconductor, Inc. 6.9 Port G The state of port G pin 7 (PG7) at reset is mode dependent. In single-chip or bootstrap modes high-impedance input; its data direction can be changed through DDRG. In expanded and special test modes, PG7 functions as the R/W line to control the direction of data flow between the MCU and external memory devices. ...

  • Page 146

    ... Freescale Semiconductor, Inc. Parallel Input/Output 6.10 Port H The state of port H pin 7 (PH7) at reset is mode dependent. In single-chip or bootstrap modes high-impedance input; its data direction can be changed through DDRH. In expanded and special test modes PH7 is the program chip select line, CSPROG at reset, but can be reconfigured for GPIO (see Port H pins (PH[6:0]) reset to high-impedance inputs in any mode ...

  • Page 147

    ... Freescale Semiconductor, Inc. 6.11 Internal Pullup Resistors M68HC11KS series devices contain selectable internal pullup resistors for ports and H. The resistors for each port are enabled by setting the corresponding bit in the PPAR register. PPAR itself must be enabled by setting the PAREN bit in the system configuration register (CONFIG) ...

  • Page 148

    ... Freescale Semiconductor, Inc. Parallel Input/Output Technical Data 148 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com M68HC11K Family MOTOROLA ...

  • Page 149

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family Section 7. Serial Communications Interface (SCI) 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 7.2 Introduction The serial communications interface (SCI universal asynchronous receiver transmitter (UART) employing a standard non-return-to-zero (NRZ) format ...

  • Page 150

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) The M68HC11K series offers several enhancements to the basic MC68HC11 SCI, including: • • • • 7.3 Data Format The SCI uses the standard non-return to zero mark/space data format illustrated in START BIT 0 BIT 1 BIT 2 BIT ...

  • Page 151

    ... Freescale Semiconductor, Inc. 6. Steps 2-5 are repeated until the entire message is sent. 7. The line returns to idle status. 7.4 Transmit Operation Transmission starts by writing a data character to the 2-byte SCI data register (SCDRH and SCDRL). The MCU parallel-loads the character into a serial shift register which shifts the data out on the transmission pin ...

  • Page 152

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Figure 7-2 TRANSMITTER SCDR Tx BUFFER BAUD RATE CLOCK 10 (11) — BIT Tx SHIFT REGISTER PARITY GENERATOR SCCR1 SCI CONTROL 1 SCI INTERRUPT SCI Rx REQUEST REQUESTS Note 1. Data direction register for port D Figure 7-2. SCI Transmitter Block Diagram ...

  • Page 153

    ... Freescale Semiconductor, Inc. 7.5 Receive Operation During receive operations, data from the TxD pin is shifted into the serial shift register. A completed word is parallel-loaded to a receive data register (RDR), which can be read through SCDRH/L. This double-buffered operation allows reception of the current character while the MCU reads the previous character ...

  • Page 154

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) • • • • • Figure 7-3 Technical Data 154 The overrun error (OR) flag is set instead of the RDRF bit when the next byte is ready to be transferred from the receive shift register to the RDR and the RDR is already full. The data in the shift register is lost and the data that was already in RDR is not disturbed ...

  • Page 155

    ... Freescale Semiconductor, Inc. RECEIVER BAUD RATE CLOCK (1) DDD0 PIN BUFFER PD0 AND CONTROL RxD DISABLE DRIVER SCSR2 SCI STATUS 2 SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Note 1. Data direction register for port D Figure 7-3. SCI Receiver Block Diagram M68HC11K Family ...

  • Page 156

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 7.6 Wakeup Feature The wakeup feature reduces SCI service overhead in multiple receiver systems system generates address information at the beginning of every message, each receiver can determine whether or not it is the intended recipient of a message by evaluating the first character(s) through software ...

  • Page 157

    ... Freescale Semiconductor, Inc. 7.7 Short Mode Idle Line Detection This feature can increase system communication speed by reducing the amount of time between messages. Setting the ILT bit in SCCR1 allows the SCI receiver to detect the consecutive idle period before the stop bit of an incoming character is received. If the last few bits of the character are 1s, they are counted as the first high bits in the frame of 1s comprising the idle period following the character ...

  • Page 158

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 7.9 SCI Registers The six addressable registers in the SCI are: • • • • • • NOTE: Throughout this manual, the registers are discussed by function. In the event that not all bits in a register are referenced, the bits that are not discussed are shaded ...

  • Page 159

    ... Freescale Semiconductor, Inc. BTST — Baud Register Test Bit BTST is for factory use only and is only accessible in special test mode. BSPL — Baud Rate Counter Split Bit BSOK is for factory use only and is only accessible in special test mode. SBR[12:0] — SCI Baud Rate Select Bits These bits represent the value BR in: EXTAL Freq ...

  • Page 160

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 7.9.2 Serial Communications Control Register 1 Address $0072 Read: Write: Reset: LOOPS — SCI Loop Mode Enable Bit Both the transmitter and receiver must be enabled to use the loop mode. When the loop mode is enabled, the TxD pin is driven high (idle line state) if the transmitter is enabled. WOMS — ...

  • Page 161

    ... Freescale Semiconductor, Inc. PE — Parity Enable Bit PT — Parity Type Bit 7.9.3 Serial Communications Control Register 2 Address $0073 Read: Write: Reset: TIE — Transmit Interrupt Enable Bit TCIE — Transmit Complete Interrupt Enable Bit RIE — Receiver Interrupt Enable Bit ILIE — Idle Line Interrupt Enable Bit ...

  • Page 162

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) TE — Transmitter Enable Bit When TE goes from one unit of idle character time (logic 1) is queued as a preamble. RE — Receiver Enable Bit RWU — Receiver Wakeup Control SBK — Send Break Bit At least one character time of break is queued and sent each time SBK is written to 1 ...

  • Page 163

    ... Freescale Semiconductor, Inc. TDRE — Transmit Data Register Empty Flag TDRE is set when the SCDR transfers its contents to the transmission shift register. TC — Transmit Complete Flag TC is set when the final character in a message has been sent (no data, preamble, or break transmissions pending). ...

  • Page 164

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) FE — Framing Error Flag FE is set when detected where a stop bit (logic 1) was expected. PF — Parity Error Flag PF is set if received data has incorrect parity. Clear PF by reading SCSR1. 7.9.5 Serial Communication Status Register 2 ...

  • Page 165

    ... Freescale Semiconductor, Inc. 7.9.6 Serial Communications Data Register The SCDR is a parallel register that performs two functions. Received data in the RDR is read from this address when the SCI is receiving, and data to be transmitted is written to this address when the SCI is transmitting. Address $0076 ...

  • Page 166

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Technical Data 166 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com M68HC11K Family MOTOROLA ...

  • Page 167

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family Section 8. Serial Peripheral Interface (SPI) 8.1 Contents 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.2 Introduction The serial peripheral interface (SPI) provides synchronous ...

  • Page 168

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) extra hardware. The SPI system can send data one half of the E-clock rate when configured as master and the full E-clock rate when configured as a slave. 8.3 SPI Functional Description The SPI is a 4-wire, full-duplex communication system. Characters are eight bits, transmitted most significant bit (MSB) first ...

  • Page 169

    ... Freescale Semiconductor, Inc. A single MCU register, the serial peripheral data register (SPDR) is used both to read input data from the read buffer and to write output data to the transmit shift register. Figure 8-1 INTERNAL MCU CLOCK DIVIDER 2 ÷ SPI CLOCK (MASTER) SELECT SPI CONTROL ...

  • Page 170

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 8.4 SPI Signal Descriptions The four basic SPI signals (MISO, MOSI, SCK, and SS) are discussed for both the master and slave modes in the following paragraphs. Every SPI output line must have its corresponding port D data direction register (DDRD) bit set ...

  • Page 171

    ... Freescale Semiconductor, Inc. 8.4.4 Slave Select (SS) The slave select (SS) input is used to target specific devices in the SPI system. It must be pulled low on a targeted slave device prior to any communication with a master and must remain low for the duration of the transaction. SS must always be high on any device in master mode. ...

  • Page 172

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) CPOL selects an active high or low clock edge. CPHA selects one of two transfer formats. When CPHA is cleared, the shift clock is ORed with SS. Each slave’s SS pin must be pulled high before it writes the next output byte to its data register slave writes to its data register while SS is low, a write collision error occurs ...

  • Page 173

    ... Freescale Semiconductor, Inc. control bits associated with the SPI are cleared, effectively forcing the pins to be high-impedance inputs. The mode fault error flag (MODF) is set in the serial peripheral status register (SPSR). An interrupt is generated, subject to masking by the SPIE control bit and the I bit in the CCR ...

  • Page 174

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) NOTE: Throughout this manual, the registers are discussed by function. In the event that not all bits in a register are referenced, the bits that are not discussed are shaded. 8.6.1 Serial Peripheral Control Register Address: $0028 ...

  • Page 175

    ... Freescale Semiconductor, Inc. CPOL — Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device has a steady state low value. When CPOL is set, SCK idles high. CPHA — Clock Phase Bit The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave ...

  • Page 176

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 8.6.2 Serial Peripheral Status Register Address: $0029 Read: Write: Reset: SPIF — SPI Transfer Complete Flag SPIF is set upon completion of data transfer between the processor and the external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated ...

  • Page 177

    ... Freescale Semiconductor, Inc. 8.6.3 Serial Peripheral Data Register The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this register initiates transmission or reception of a byte, and this only occurs in the master device. At the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave devices ...

  • Page 178

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 8.6.4 Port D Data Direction Register Address: $0009 Read: Write: Reset: DDD5 Bit Bit 5 of the port D data register (PD5) is dedicated as the slave select (SS) input. In SPI slave mode, DDD5 has no meaning or effect. In SPI master mode, DDD5 affects PD5 as follows: ...

  • Page 179

    ... Freescale Semiconductor, Inc. 8.6.5 System Configuration Options 2 Address: $0038 Read: Write: Reset: 1. Not available on M68HC11K devices Figure 8-7. System Configuration Options 2 Register (OPT2) LSBF — Least Significant Bit First Enable Bit Setting LSBF causes data to be transmitted LSB first (the default is MSB first). LSBF does not affect bit positions in the data register ...

  • Page 180

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Technical Data 180 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com M68HC11K Family MOTOROLA ...

  • Page 181

    ... Freescale Semiconductor, Inc. Technical Data — M68HC11K Family 9.1 Contents 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.6.6 9.6.7 9.6.8 9.7 9.7.1 9.7.2 9.7.3 M68HC11K Family MOTOROLA For More Information On This Product, Section 9 ...

  • Page 182

    ... Freescale Semiconductor, Inc. Timing System 9.7.4 9.7.5 9.8 9.8.1 9.8.2 9.8.3 9.9 9.9.1 9.9.2 9.9.2.1 9.9.2.2 9.9.2.3 9.9.2.4 9.9.2.5 9.9.2.6 9.9.2.7 9.2 Introduction M68HC11 microcontrollers contain an extensive timing system to support a wide variety of timer-related functions. This section discusses the nature of the timing system and presents details of timer-related functions including: • ...

  • Page 183

    ... Freescale Semiconductor, Inc. 9.3 Timer Structure As Figure 9-1 and the internal PH2 bus clock, are derived from the oscillator output divided by four. EXTAL OSCILLATOR 4 PRESCALER ( 16, 32, 64, 128) SPR[2:0] PRESCALER ( 16) PR[1:0] TCNT IC/OC Figure 9-1. Timer Clock Divider Chains M68HC11K Family MOTOROLA ...

  • Page 184

    ... Freescale Semiconductor, Inc. Timing System The PH2 bus clock feeds four primary divider chains. The functions supplied by each of these chains are: 1. Serial peripheral interface (SPI) 2. Input capture/output compare (IC/OC) 3. Pulse accumulator (PA) 4. RTI and COP watchdog circuit The SPI prescale factor is determined by bits SPR[2] in the system configuration options 2 (OPT2) register and SPR[1:0] in the serial peripheral control register (SPCR) ...

  • Page 185

    ... Freescale Semiconductor, Inc. The free-running counter begins incrementing from $0000 as the MCU comes out of reset and continues to the maximum count, $FFFF. At the maximum count, the counter rolls over to $0000, sets the timer overflow flag (TOF) in the timer interrupt flag 2 (TFLG2) register, and continues to increment ...

  • Page 186

    ... Freescale Semiconductor, Inc. Timing System Figure 9-2 A pin control block includes logic for timer functions and for general-purpose I/O. This block contains the edge-detection logic for pins PA[2:0] as well as the control logic that enables edge selection for the input capture trigger. ...

  • Page 187

    ... Freescale Semiconductor, Inc. PRESCALER — DIVIDE SYSTEM PR1 PR0 CLOCK 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO) 16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH CLK I4/O5 16-BIT LATCH CLK TIC1 (HI) ...

  • Page 188

    ... Freescale Semiconductor, Inc. Timing System 9.4.1 Timer Counter Register Address: $000E — TCNT (High) Read: Write: Reset: Address: $000F — TCNT (Low) Read: Write: Reset: TCNT reflects the current value in the free-running counter. Input capture functions use this number to mark the time of an external event, and output compare functions use it to determine the time at which to generate an event ...

  • Page 189

    ... Freescale Semiconductor, Inc. 9.4.2 Timer Interrupt Flag 2 Register Address: $0025 Read: Write: Reset: Clear each flag by writing the corresponding bit position. TOF — Timer Overflow Flag Set when TCNT changes from $FFFF to $0000. 9.4.3 Timer Interrupt Mask 2 Register Address: $0024 Read: ...

  • Page 190

    ... Freescale Semiconductor, Inc. Timing System PR[1:0] — Timer Prescaler Select Bits These bits determine the main timer prescale divisor, as shown in Table number to produce the clock which drives the free-running counter. Refer to In normal modes, PR[1:0] can be written only once, and the write must be within 64 cycles after reset ...

  • Page 191

    ... Freescale Semiconductor, Inc. 9.4.5 Pulse Accumulator Control Register Address: $0026 Read: Write: Reset: Figure 9-7. Pulse Accumulator Control Register (PACTL) I4/O5 — Input Capture 4/Output Compare 5 Bit To configure PA3 as input compare 4, clear DDA3 and set I4/05. To configure PA3 as output compare 5, set DDA3 and clear I4/05. If the DDA3 bit is set (configuring PA3 as an output) and IC4 is enabled, writing a one to TI4/O5 causes an input capture ...

  • Page 192

    ... Freescale Semiconductor, Inc. Timing System 9.5.1 Timer Input Capture Registers Address: $0010 — TIC1 (High) Read: Write: Reset: Address: $0011 — TIC1 (Low) Read: Write: Reset: Address: $0012 — TIC2 (High) Read: Write: Reset: Address: $0013 — TIC2 (Low) Read: Write: Reset: Address: $0014— ...

  • Page 193

    ... Freescale Semiconductor, Inc. 9.5.2 Timer Input Capture 4/Output Compare 5 Register Address: $001E — TI4/O5 (High) Read: Write: Reset: Address: $001F — TI4/O5 (Low) Read: Write: Reset: TI4/05 functions as the input capture register for IC4 when PA3 is configured for input capture 4. When an edge on an input capture pin has been detected and synchronized, the 16-bit free-running counter value is latched in the associated input capture register pair in a single 16-bit parallel transfer ...

  • Page 194

    ... Freescale Semiconductor, Inc. Timing System 9.5.3 Timer Interrupt Flag 1 Register Address: $0023 Read: Write: Reset: Clear each flag by writing the corresponding bit position. ICxF — Input Capture x Flag Set each time a selected active edge is detected on the corresponding input capture line. I4/O5F — Input Capture 4/Output Compare 5 Flag Set each time a selected active edge is detected on the IC4 line if IC4 is enabled ...

  • Page 195

    ... Freescale Semiconductor, Inc. I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable Bit If I4/O5I is set when IC4 is enabled and the I4/O5F flag bit is set, a hardware interrupt sequence is requested. 9.5.5 Timer Control 2 Register Address: $0021 Read: Write: Reset: EDGx[B:A] — Input Capture Edge Control Bits These bit pairs determine the edge polarities on the input capture pins that trigger the corresponding input capture functions ...

  • Page 196

    ... Freescale Semiconductor, Inc. Timing System 9.6 Output Compare (OC) The output compare (OC) function generates a programmed action when the 16-bit counter reaches a specified value. Each of the five output compare functions contains a separate 16-bit timer output compare (TOC) register and a dedicated 16-bit comparator. Each TOC register is set to $FFFF on reset ...

  • Page 197

    ... Freescale Semiconductor, Inc. • Because the pin state changes occur at specific values of the free-running counter, the pulse width can be controlled accurately to the resolution of the free-running counter, independent of software latencies. To generate an output signal of a specific frequency and duty cycle, repeat this pulse-generating procedure. ...

  • Page 198

    ... Freescale Semiconductor, Inc. Timing System Address: $001A— TOC3 (High) Read: Write: Reset: Address: $001B — TOC3 (Low) Read: Write: Reset: Address: $001C— TOC4 (High) Read: Write: Reset: Address: $001D — TOC4 (Low) Read: Write: Reset: All output compare registers are 16-bit read-write. Any of these registers can be used as a storage location not used for output compare or input capture ...

  • Page 199

    ... Freescale Semiconductor, Inc. 9.6.2 Timer Input Capture 4/Output Compare 5 Register Address: $001E — TI4/O5 (High) Read: Write: Reset: Address: $001F — TI4/O5 (Low) Read: Write: Reset: Functions as the output compare register for OC5 when PA3 is configured for output compare 5. This register is 16-bit read-write. It can be used as a storage location not used for output compare or input capture ...

  • Page 200

    ... Freescale Semiconductor, Inc. Timing System 9.6.4 Timer Interrupt Mask 1 Register Address: $0022 Read: Write: Reset: Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. OC1I–OC4I — Output Compare x Interrupt Enable Bits If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested. I4/O5I — ...