MC68HC908JB16DW Freescale Semiconductor, MC68HC908JB16DW Datasheet - Page 323

• Manufacturer Part Number: MC68HC908JB16DW
• Description: IC MCU 16K FLASH 6MHZ USB 28SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB16DW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

MC68HC908JB16
Freescale Semiconductor
Output capacitive load
PLL frequency list
Rx LO 1
Rx LO 2
Rx LO 3
Rx LO 4
Rx LO 5
PLL output signal frequency
accuracy
PLL output signal phase
noise level
VCO frequency range
PLL lock duration
Duration for Lock bit detection
PLL stop duration
PLL output sideband
noise level
PLL output channel
intermodulation products
Notes:
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Defined as the total time for PLL module switching from channel-to-channel and the frequency is stable with ±60ppm. The
4. Defined as the total time for PLL module active from wait/stop mode to the frequency is stable with ±60ppm error. The
5. Defined as the total time for PLL Lock bit setup from un-lock to lock state with the frequency is stable with ±10% error. The
6. Side-band component generate from reference frequency modulation on carrier.
7. Noise component generate from adjacent channel carrier when both PLLs are enable.
(see
reference frequency should be greater than 32kHz.
reference frequency should be greater than 32kHz.
reference frequency should be greater than 32kHz.
DDA
Characteristic
13.10 Pre-Defined VCO Output Frequency
= 4.0 to 5.5 Vdc, V
(6)
—
Rev. 1.1
(1)
(7)
SSA
= 0 Vdc, T
At offset >42.5kHz
At offset >42.5kHz
Wait/stop mode to
Within ±10% final
PLL module from
active to disable
At ±1kHz offset
At offset >4kHz
Exclude crystal
OSC tolerance
frequency
from carrier
Condition
channel to
channel
A
active
mode.
= T
L
Electrical Specifications
to T
(4)
(3)
(5)
H
Settings) and under steady state condition, unless otherwise noted.
, with the pre-defined programming setting for the PLL
Symbol
C
L
Min
26
—
—
—
—
—
—
—
—
—
—
Typ
26.54
26.59
26.64
26.69
26.74
±100
–40
–40
–50
–50
±4
10
20
10
—
—
—
(2)
Electrical Specifications
Max
10
28
—
—
—
—
—
—
—
—
1
Technical Data
dBc/Hz
MHz
MHz
Unit
ppm
dBc
dBc
ms
ms
ms
ms
pF
Hz
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