MC68HC908JB16DW Freescale Semiconductor, MC68HC908JB16DW Datasheet - Page 91

• Manufacturer Part Number: MC68HC908JB16DW
• Description: IC MCU 16K FLASH 6MHZ USB 28SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB16DW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

MC68HC908JB16
Freescale Semiconductor
SWI
TAP
TAX
TPA
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSX
TXA
TXS
A
C
CCR Condition code register
dd
dd rr
DD
DIR
DIX+ Direct to indexed with post increment addressing mode
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D Indexed with post increment to direct addressing mode
IX1
IX1+
IX2
M
N
Source
Form
Accumulator
Carry/borrow bit
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
Software Interrupt
Transfer A to CCR
Transfer A to X
Transfer CCR to A
Test for Negative or Zero
Transfer SP to H:X
Transfer X to A
Transfer H:X to SP
—
Rev. 1.1
Operation
Table 6-1. Instruction Set Summary (Sheet 8 of 8)
Central Processor Unit (CPU)
(A) – $00 or (X) – $00 or (M) – $00
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; I ← 1
(SP) ← (H:X) – 1
H:X ← (SP) + 1
Description
CCR ← (A)
A ← (CCR)
X ← (A)
A ← (X)
n
opr
PC
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP
U
V
X
Z
&
|
⊕
( )
–( )
#
«
←
?
:
—
Any bit
Operand (one or two bytes)
Program counter
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
V H I N Z C
– – 1 – – – INH
– – – – – – INH
– – – – – – INH
0 – –
– – – – – – INH
– – – – – – INH
– – – – – – INH
Effect on
CCR
Central Processor Unit (CPU)
–
INH
DIR
INH
INH
IX1
IX
SP1
Technical Data
9E6D
3D
4D
5D
6D
7D
83
84
97
85
95
9F
94
dd
ff
ff
91
9
2
1
1
3
1
1
3
2
4
2
1
2