DS87C550-QCL+ Maxim Integrated Products, DS87C550-QCL+ Datasheet - Page 40

• Manufacturer Part Number: DS87C550-QCL+
• Description: IC MCU EPROM ADC/PWM HS 68-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 87Cr

Specifications of DS87C550-QCL+

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC, 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters
as such devices, using the same symbols. The following is an explanation of the symbols.
POWER CYCLE TIMING CHARACTERISTICS
NOTES FOR POWER CYCLE TIMING CHARACTERISTICS
1. Start-up time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz
2.
EPROM PROGRAMMING AND VERIFICATION
NOTES FOR EPROM PROGRAMMING AND VERIFICATION
1. All voltage referenced to ground.
2.
PARAMETER
Cycle Start-up Time
Power-on Reset Delay
PARAMETER
Programming Voltage
Programming Supply Current
Oscillator Frequency
POR Delay
Address Setup to
Address Hold after
Data Setup to
Data Hold after
Enable High to V
V
V
Address to Data Valid
Enable Low to Data Valid
Data Float after Enable
PROG
PROG
PP
PP
crystal manufactured by Fox.
Reset delay is a synchronous counter of crystal oscillations after crystal start-up. At 33MHz, this time is 1.99
ms.
The microcontroller holds itself in reset for this duration when power is applied. No signals should be
manipulated during this interval since the microcontroller is ignoring inputs. At a 4MHz oscillator frequency,
this period is 16.4ms.
Setup to
Hold after
t
A
C
D
H
L
I
P
Width
High to
PROG
PROG
Time
Address
Clock
Logic level high
Logic level low
Instruction
Input data
PROG
PSEN
PROG
PROG
PP
PROG
PROG
Low
Low
Low
Low
SYMBOL
SYMBOL
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
DELAY
GHAX
GHDX
AVQV
t
t
AVGL
DVGL
GLGH
GHGL
V
EHSH
SHGL
GHSL
ELQV
EHQZ
I
CSU
POR
CLCL
PP
PP
40 of 49
MIN
65536
48t
48t
48t
48t
48t
MIN
12.5
10
10
90
10
4
0
CLCL
CLCL
CLCL
CLCL
CLCL
Q
R
V
W
X
Z
TYP
TYP
1.8
Output data
Valid
No longer a valid logic level
Tri-state
RD
WR
signal
signal
MAX
48t
48t
48t
65536
MAX
13.0
110
75
6
CLCL
CLCL
CLCL
UNITS NOTES
UNITS
MHz
t
t
CLCL
mA
CLCL
ms
µs
µs
µs
µs
V
NOTES
1
2
1
2