IC WIRELESS USB 2.4GHZ 28-SOIC

CYWUSB6934-28SEC

Manufacturer Part NumberCYWUSB6934-28SEC
DescriptionIC WIRELESS USB 2.4GHZ 28-SOIC
ManufacturerCypress Semiconductor Corp
CYWUSB6934-28SEC datasheets
 


Specifications of CYWUSB6934-28SEC

Frequency2.4GHzData Rate - Maximum62.5kbps
Modulation Or ProtocolDSSS, GFSKApplicationsHID, PC, Peripheral Gaming Devices
Power - Output0dBmSensitivity-90dBm
Voltage - Supply2.7 V ~ 3.6 VData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature0°C ~ 70°C
Package / Case28-SOICOperating Temperature (min)0C
Operating Temperature (max)70COperating Temperature ClassificationCommercial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (typ)3V
Operating Supply Voltage (max)3.6VLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Memory Size-Current - Transmitting-
Current - Receiving-Other names428-1580-5
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Addr: 0x07
7
6
Underflow B
Overflow B
EOF B
Bit
Name
Description
7
Underflow B
The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES
Data B register (Reg 0x0B)
1 = Underflow B interrupt enabled for Receive SERDES Data B
0 = Underflow B interrupt disabled for Receive SERDES Data B
An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when it is
empty.
6
Overflow B
The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data
B register (Reg 0x0B)
1 = Overflow B interrupt enabled for Receive SERDES Data B
0 = Overflow B interrupt disabled for Receive SERDES Data B
An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg 0x0B)
before the prior data is read out.
5
EOF B
The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.
1 = EOF B interrupt enabled for Channel B Receiver.
0 = EOF B interrupt disabled for Channel B Receiver.
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been
detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field. If 0 is the EOF
length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the
receive status register
4
Full B
The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B) having
data placed in it.
1 = Full B interrupt enabled for Receive SERDES Data B
0 = Full B interrupt disabled for Receive SERDES Data B
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B
register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not
a complete byte has been received.
3
Underflow A
The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES
Data A register (Reg 0x09)
1 = Underflow A interrupt enabled for Receive SERDES Data A
0 = Underflow A interrupt disabled for Receive SERDES Data A
An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when it is
empty.
2
Overflow A
The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data
A register (0x09)
1 = Overflow A interrupt enabled for Receive SERDES Data A
0 = Overflow A interrupt disabled for Receive SERDES Data A
An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg 0x09)
before the prior data is read out.
1
EOF A
The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel A
Receiver.
1 = EOF A interrupt enabled for Channel A Receiver.
0 = EOF A interrupt disabled for Channel A Receiver.
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been
detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field. If 0 is the EOF
length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the receive
status register.
0
Full A
The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having data
written into it.
1 = Full A interrupt enabled for Receive SERDES Data A
0 = Full A interrupt disabled for Receive SERDES Data A
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A
register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not
a complete byte has been received.
Document 38-16007 Rev. *G
REG_RX_INT_EN
5
4
3
Full B
Underflow A
Figure 7-6. Receive SERDES Interrupt Enable
CYWUSB6932
CYWUSB6934
Default: 0x00
2
1
0
Overflow A
EOF A
Full A
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