IC WIRELESS USB 2.4GHZ 28-SOIC

CYWUSB6934-28SEC

Manufacturer Part NumberCYWUSB6934-28SEC
DescriptionIC WIRELESS USB 2.4GHZ 28-SOIC
ManufacturerCypress Semiconductor Corp
CYWUSB6934-28SEC datasheets
 


Specifications of CYWUSB6934-28SEC

Frequency2.4GHzData Rate - Maximum62.5kbps
Modulation Or ProtocolDSSS, GFSKApplicationsHID, PC, Peripheral Gaming Devices
Power - Output0dBmSensitivity-90dBm
Voltage - Supply2.7 V ~ 3.6 VData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature0°C ~ 70°C
Package / Case28-SOICOperating Temperature (min)0C
Operating Temperature (max)70COperating Temperature ClassificationCommercial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (typ)3V
Operating Supply Voltage (max)3.6VLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Memory Size-Current - Transmitting-
Current - Receiving-Other names428-1580-5
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Addr: 0x1D
7
6
Bit
Name
Description
These bits are reserved. This register is read-only.
7:1
Reserved
0
Wakeup Status
Wakeup status.
0 = Wake interrupt not pending
1 = Wake interrupt pending
This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register (Reg
0x1D). This register is read-only.
Addr: 0x20
7
6
Reg Write
MID Read
Reserved
Control
Enable
Bit
Name
Description
This bit is reserved and should be written with zero.
7
Reserved
6
Reg Write Control
Enables write access to Reg 0x2E and Reg 0x2F.
1 = Enables write access to Reg 0x2E and Reg 0x2F
0 = Reg 0x2E and Reg 0x2F are read-only
5
MID Read Enable
The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when reading
the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
1 = Enables read of MID registers
0 = Disables read of MID registers
4:3
Reserved
These bits are reserved and should be written with zeroes.
2
PA Output Enable The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier.
1 = PA Control Output Enabled on PACTL pin
0 = PA Control Output Disabled on PACTL pin
1
PA Invert
The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PA Output Enable bit is
set high. PA Output Enable and PA Invert cannot be simultaneously changed.
1 = PACTL active low
0 = PACTL active high
0
Reset
The Reset bit is used to generate a self-clearing device reset.
1 = Device Reset. All registers are restored to their default values.
0 = No Device Reset.
Document 38-16007 Rev. *G
REG_WAKE_STAT
5
4
3
Reserved
Figure 7-20. Wake Status
REG_ANALOG_CTL
5
4
3
Reserved
Reserved
Figure 7-21. Analog Control
CYWUSB6932
CYWUSB6934
Default: 0x01
2
1
0
Wakeup Status
Default: 0x00
2
1
0
PA Output
PA Invert
Reset
Enable
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