IC WIRELESS USB 2.4GHZ 28-SOIC

CYWUSB6934-28SEC

Manufacturer Part NumberCYWUSB6934-28SEC
DescriptionIC WIRELESS USB 2.4GHZ 28-SOIC
ManufacturerCypress Semiconductor Corp
CYWUSB6934-28SEC datasheets
 


Specifications of CYWUSB6934-28SEC

Frequency2.4GHzData Rate - Maximum62.5kbps
Modulation Or ProtocolDSSS, GFSKApplicationsHID, PC, Peripheral Gaming Devices
Power - Output0dBmSensitivity-90dBm
Voltage - Supply2.7 V ~ 3.6 VData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature0°C ~ 70°C
Package / Case28-SOICOperating Temperature (min)0C
Operating Temperature (max)70COperating Temperature ClassificationCommercial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (typ)3V
Operating Supply Voltage (max)3.6VLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Memory Size-Current - Transmitting-
Current - Receiving-Other names428-1580-5
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Addr: 0x19
7
6
Reserved
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6:0
Threshold Low
The Threshold Low value is used to determine the number of missed chips allowed when attempting to correlate a
single data bit of value ‘0’. A perfect reception of a data bit of ‘0’ with a 64 chips/bit PN code would result in zero
correlation matches, meaning the exact inverse of the PN code has been received. By setting the Threshold Low
value to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data
bit. This value along with the Threshold High value determine the correlator count values for logic ‘1’ and logic ‘0’.
The threshold values used determine the sensitivity of the receiver to interference and the dependability of the
received data. By allowing a minimal number of erroneous chips the dependability of the received data increases
while the robustness to interference decreases. On the other hand increasing the maximum number of missed chips
means reduced data integrity but increased robustness to interference and increased range.
Addr: 0x1A
7
6
Reserved
Bit
Name
Description
This bit is reserved and should be written with zero.
7
Reserved
The Threshold High value is used to determine the number of matched chips allowed when attempting to correlate
6:0
Threshold High
a single data bit of value ‘1’. A perfect reception of a data bit of ‘1’ with a 64 chips/bit or a 32 chips/bit PN code would
result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received perfectly. By
setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be erroneous while still identifying
the value of the received data bit. This value along with the Threshold Low value determine the correlator count
values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the receiver to interference
and the dependability of the received data. By allowing a minimal number of erroneous chips the dependability of
the received data increases while the robustness to interference decreases. On the other hand increasing the
maximum number of missed chips means reduced data integrity but increased robustness to interference and
increased range.
Addr: 0x1C
7
6
Bit
Name
Description
These bits are reserved and should be written with zeroes.
7:1
Reserved
0
Wakeup Enable
Wakeup interrupt enable.
0 = disabled
1 = enabled
A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications.
Document 38-16007 Rev. *G
REG_THRESHOLD_L
5
4
3
Threshold Low
Figure 7-17. Threshold Low
REG_THRESHOLD_H
5
4
3
Threshold High
Figure 7-18. Threshold High
REG_WAKE_EN
5
4
3
Reserved
Figure 7-19. Wake Enable
CYWUSB6932
CYWUSB6934
Default: 0x08
2
1
0
Default: 0x38
2
1
0
Default: 0x00
2
1
0
Wakeup En-
able
Page 17 of 30