MCIMX253CVM4 Freescale Semiconductor, MCIMX253CVM4 Datasheet - Page 67

• Manufacturer Part Number: MCIMX253CVM4
• Description: IC MPU I.MX25 IND 400MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX25r

Specifications of MCIMX253CVM4

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: External Program Memory
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.52 V
• Data Converters: A/D 3x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-LFBGA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

1
2
3
Freescale Semiconductor
1
DQ Slew Rate
DDR24 DQS - DQ Skew (defines the Data valid window in read cycles related to DQS)
DDR25 DQS DQ in HOLD time from DQS
DDR26 DQS output access time from SDCLK posedge
All units in ‘ps’.
Test conditions are at capacitance=15pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for
address and controls.
SDRAM CLK and DQS related parameters are measured from the 50% point. That is, high is defined as 50% of the signal
value, and low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of
SDCLK and SDCLK (inverted clock).
Test conditions are at capacitance=15 pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for
address and controls.
ID
V/ns
DQS (input)
SDCLK_B
DQ (input)
SDCLK
Table 51. tDS1, tDH1 Derating Values for DDR2-400, DDR2-533
2.0 188
1.5 146
1.0 63
0.9
0.8
0.7
0.6
0.5
0.4
Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram
—
—
—
—
—
—
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
188 167 146 125
167 125 125
125
—
—
—
—
—
—
Table 52. DDR2 SDRAM Read Cycle Parameter Table
DDR26
42
31
—
—
—
—
—
83
69
—
—
—
—
—
DDR24
DATA
3
–11 –14 –13 –13 –18 –27 –29 –45
–25 –31 –27 –30 –32 –44 –43 –62 –60 –86
83
—
—
—
—
0
Parameter
63
42
—
—
—
—
0
DATA
–45 –53 –50 –67 –61 –85 –78 –109 –108 –152
81
–2
—
—
—
—
DQS Single-Ended Slew Rate
DDR25
43
—
—
—
—
1
DATA
–74 –96 –85 –114 –102 –138 –132 –181 –183 –246
—
—
–7
—
—
DATA
–13
—
—
—
—
–128 –156 –145 –180 –175 –223 –226 –288
—
—
—
—
DATA
—
—
—
—
–210 –243 –240 –286 –291 –351
1,2,3
—
—
—
—
DATA
1,2
Symbol
(continued)
t
—
—
—
—
t
DQSCK
DQSQ
t
QH
DATA
—
—
—
—
—
2.925
Min. Max.
–0.5
DDR2-400
—
—
—
—
—
—
DATA
0.35
0.5
—
—
—
—
—
—
—
Unit
ns
ns
ns
—
—
—
—
—
—
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