MCIMX253CVM4 Freescale Semiconductor, MCIMX253CVM4 Datasheet - Page 98

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MCIMX253CVM4

Manufacturer Part Number
MCIMX253CVM4
Description
IC MPU I.MX25 IND 400MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Datasheets

Specifications of MCIMX253CVM4

Core Processor
ARM9
Core Size
32-Bit
Speed
400MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
External Program Memory
Ram Size
144K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.52 V
Data Converters
A/D 3x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
400-LFBGA
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX253CVM4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
SIMx_DATAy_RX_TX
3.7.14.1
SIM cards may have internal reset, or active low reset. The following subset describes the reset sequences
in these two cases.
3.7.14.1.1
Figure 69
following steps:
Table 73
3.7.14.1.2
Figure 70
following steps:
98
SIMn_SVENm
SIMx_CLKy
After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.
The card must send a response on SIMx_DATAy_RX_TX acknowledging the reset between
400–40000 clock cycles after T0.
After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.
SIMx_RSTy must remain low for at least 40,000 clock cycles after T0 (no response is to be
received on RX during those 40,000 clock cycles)
SIMx_RSTy is asserted (at time T1)
SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be
received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1.
defines the general timing requirements for the SIM interface.
shows the reset sequence for SIM cards with active low reset. The reset sequence comprises the
shows the reset sequence for SIM cards with internal reset. The reset sequence comprises the
Ref No.
SIM Reset Sequences
1
2
SIM Cards with Internal Reset
SIM Cards with Active Low Reset
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
T0
Table 73. Timing Specifications, Internal Reset Card Reset Sequence
1
Figure 69. Internal Reset Card Reset Sequence
2
Min.
400
RESPONSE
40,000
Max.
200
Freescale Semiconductor
clk cycles
clk cycles
Units

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