MCIMX253CVM4 Freescale Semiconductor, MCIMX253CVM4 Datasheet - Page 87

• Manufacturer Part Number: MCIMX253CVM4
• Description: IC MPU I.MX25 IND 400MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX25r

Specifications of MCIMX253CVM4

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: External Program Memory
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.52 V
• Data Converters: A/D 3x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-LFBGA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

3.7.9.1.5
The transmitter functions correctly up to an FEC_TX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
FEC_TX_CLK frequency.
Figure 56
in the figure.
1
3.7.9.1.6
Figure 57
the figure.
Freescale Semiconductor
M5
M6
M7
M8
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
ID
FEC_TXD[3:0] (outputs)
FEC_TX_CLK (input)
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
FEC_TX_CLK pulse width high
FEC_TX_CLK pulse width low
shows MII asynchronous input timings.
shows MII transmit signal timings.
FEC_CRS, FEC_COL
FEC_TX_EN
FEC_TX_ER
MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK)
MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
Figure 56. MII Transmit Signal Timing Diagram
Figure 57. MII Async Inputs Timing Diagram
Characteristic
Table 61. MII Transmit Signal Timing
1
Table 61
M5
Table 62
M6
M7
describes the timing parameters (M5–M8) shown
describes the timing parameter (M9) shown in
M9
Min.
35%
35%
—
M8
5
Max.
65%
65%
—
20
FEC_TX_CLK period
FEC_TX_CLK period
Unit
ns
ns
87