MCIMX253CVM4 Freescale Semiconductor, MCIMX253CVM4 Datasheet - Page 103

• Manufacturer Part Number: MCIMX253CVM4
• Description: IC MPU I.MX25 IND 400MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX25r

Specifications of MCIMX253CVM4

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: External Program Memory
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.52 V
• Data Converters: A/D 3x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-LFBGA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

3.7.16
Figure 76
Table 80
Freescale Semiconductor
describe the timing parameters shown in the respective figures.
LCD_CLK (LCD_DATA[6])
and
LCD_CLK (LCD_DATA[6])
LCD_CLK (LCD_DATA[6])
LCD_CLK (LCD_DATA[6])
Smart Liquid Crystal Display Controller (SLCDC)
SDATA (LCD_DATA[7])
SDATA (LCD_DATA[7])
SDATA (LCD_DATA[7])
SDATA (LCD_DATA[7])
Figure 77
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Figure 76. SLCDC Timing Diagram—Serial Transfers to LCD Device
LCD_CS
LCD_CS
LCD_CS
LCD_CS
show SLCDC timing for serial and parallel transfers respectively.
RS
RS
RS
RS
tcss
tcss
tcss
(This diagram shows the case SCKPOL = 1, CSPOL = 0)
tcss
(This diagram shows the case SCKPOL = 0, CSPOL = 0)
(This diagram shows the case SCKPOL = 0, CSPOL = 1)
(This diagram shows the case SCKPOL = 1, CSPOL = 1)
MSB
MSB
MSB
MSB
RS=0 => command data, RS=1=> display data
RS=0 => command data, RS=1=> display data
RS=0 => command data, RS=1=> display data
RS=0 => command data, RS=1=> display data
tcyc
tcyc
tcyc
tcyc
tds
tds
tds
tds
trss
trss
trss
trss
tcl
tcl
tcl
tcl
tch
tdh
tch
tdh
tch
tdh
tch
tdh
tcsh
tcsh
tcsh
tcsh
LSB
LSB
LSB
LSB
trsh
trsh
trsh
trsh
Table 79
and
103