MCIMX253CVM4 Freescale Semiconductor, MCIMX253CVM4 Datasheet - Page 56

• Manufacturer Part Number: MCIMX253CVM4
• Description: IC MPU I.MX25 IND 400MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX25r

Specifications of MCIMX253CVM4

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: External Program Memory
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.52 V
• Data Converters: A/D 3x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-LFBGA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

1
2
3
4
5
3.7.6
The EMI module includes the enhanced SDRAM/LPDDR memory controller (ESDCTL), NAND Flash
controller (NFC), and wireless external interface module (WEIM). The following subsections give timing
information for these submodules.
56
The output SCLK transition time is tested with 25 pF drive.
T
T
T
T
wait
sclk
per
ipg
t10
t11
t12
t13
t14
ID
t1’
t2’
t3’
t5’
t6’
t7’
t1
t2
t3
t4
t5
t6
t7
t8
t9
= CSPI main clock IPG_CLOCK period
= CSPI reference baud rate clock period (PERCLK2)
= Wait time, as specified in the sample period control register
= CSPI clock period
CSPI master SCLK cycle time
CSPI master SCLK high time
CSPI master SCLK low time
CSPI slave SCLK cycle time
CSPI slave SCLK high time
CSPI slave SCLK low time
CSPI SCLK transition time
SSn output pulse width
SSn input pulse width
SSn output asserted to first SCLK edge (SS output setup
time)
SSn input asserted to first SCLK edge (SS input setup
time)
CSPI master: Last SCLK edge to SSn negated (SS
output hold time)
CSPI slave: Last SCLK edge to SSn negated (SS input
hold time)
CSPI master: CSPI1_RDY low to SSn asserted
(CSPI1_RDY setup time)
CSPI master: SSn negated to CSPI1_RDY low
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Pause between data word
External Memory Interface (EMI) Timing
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Parameter Description
Table 43. CSPI Interface Timing Parameters
Symbol
t
t
t
t
t
t
t
Sdatao
Hdatao
t
t
t
t
t
t
Sdatai
Hdatai
t
t
t
pause
clkoH
Wsso
t
t
clkoL
t
clkiH
Wssi
Ssso
Hsso
clkiL
t
Srdy
Hrdy
Sssi
Hssi
clko
clki
pr
1
(t
t
2T
t
clkoL
clkoL
clkiL
t
clkiL
Minimum
sclk
T
ipg
3T
2T
22.65
22.47
2T
T
or t
T
or t
60.2
60.2
30.1
30.1
or t
T
2.6
2
30
per
or t
ipg
per
0
0
0
+ 0.5
sclk
sclk
+T
per
clkiH
clkoH
clkoH
5
4
clkiH
wait
) –
or
3
or
Freescale Semiconductor
Maximum
5T
8.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
per
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—