MCIMX253CVM4 Freescale Semiconductor, MCIMX253CVM4 Datasheet - Page 47

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MCIMX253CVM4

Manufacturer Part Number
MCIMX253CVM4
Description
IC MPU I.MX25 IND 400MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Datasheets

Specifications of MCIMX253CVM4

Core Processor
ARM9
Core Size
32-Bit
Speed
400MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
External Program Memory
Ram Size
144K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.52 V
Data Converters
A/D 3x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
400-LFBGA
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX253CVM4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
To meet PIO write mode timing requirements, a number of timing parameters must be controlled.
shows timing parameters and their determining relations, and indicates parameters that can be adjusted to
meet required conditions.
1
3.7.2.2
Figure 13
Freescale Semiconductor
Parameter
See
ATA
tA
t1
t2
t9
t3
t4
t0
Figure
and
Mode Timing
12.
Parameter
Multiword DMA (MDMA) Mode Timing
PIO Write
Figure 14
t2w
tA
t1
t9
t4
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
1
READ Data(15:0)
t1(min.) = time_1 × T – (tskew1 + tskew2 + tskew5)
t2(min.) = time_2w × T – (tskew1 + tskew2 + tskew5)
t9(min.) = time_9 × T – (tskew1 + tskew2 + tskew6)
t3(min.) = (time_2w – time_on) × T – (tskew1 + tskew2 +tskew5)
t4(min.) = time_4 × T – tskew1
tA = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2 × tbuf)
t0(min.) = (time_1 + time_2 + time_9) × T
Avoid bus contention when switching buffer on by making ton long
enough
Avoid bus contention when switching buffer off by making toff long
enough
show the timing for MDMA read and write modes, respectively.
ADDR
(See note 1)
Table 37. Timing Parameters for PIO Write Mode
DMACK
DMARQ
DIOR
Figure 13. MDMA Read Mode Timing
tm
te
tgr
td
Relation
tk
tfr
tk1
tkjn
if not met, increase time_2w
Adjustable Parameter(s)
time_1, time_2r, time_9
time_2w
time_ax
time_9
time_4
time_1
Table 37
47

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