NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 40

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

An internal Slow Timer Clock is supplied to automatically control features that happen over a relatively long period of
time, or time-spans. This enables the NAU8812 to implement long time-span features without any host/processor
management or intervention.
The Slow Timer Clock supports two features automatic time out for the zero-crossing holdoff of PGA volume
changes, and timing for debouncing of the mechanical jack detection feature. If either feature is required, the Slow
Timer Clock must be enabled. The Slow Timer Clock is initialized in the disabled state.
The Slow Timer Clock rate is derived from MCLK using an integer divider that is compensated for the sample rate as
indicated by the register address (0x07). If the sample rate register value precisely matches the actual sample rate,
then the internal Slow Timer Clock rate will be a constant value of 128ms. If the actual sample rate is, for example,
44.1kHz and the sample rate selected in register 0x07 is 48kHz, the rate of the Slow Timer Clock will be
approximately 10% slower in direct proportion of the actual vs. indicated sample rate. This scale of difference should
not be important in relation to the dedicated end uses of the Slow Timer Clock.
Jack detect is a specific GPIO function. Jack detect is only available in 2-Wire mode only. Jack detect is selected by
setting GPIOSEL[2:0] address (0x08) to “001”. The GPIOPL[3] bit address (0x08) inverts the CSb/GPIO pin when set
to 1. The table below shows all the combinations for jack insert detects.
The CSb/GPIO pin has an internal de-bounce circuit so that when the jack detect feature is enabled it does not toggle
multiple times due to input glitches. Slow clock mode must be enabled when using jack insert detect by setting
SCLKEN[0] address (0x07).
emPowerAudio
Datasheet Revision 2.0
0x08
0x07
Addr
12.7.1. Slow Timer Clock
12.7.2. Jack Detect
™
D8
0
0
GPIOPL
0
0
1
1
D7
0
0
CSb/GPIO
0
1
0
1
D6
0
0
Table 19: General Purpose Control
Table 20: Jack Insert Detect mode
NSPKEN/
PSPKEN
GPIOPLL[1:0]
D5
0
Page 40 of 109
X
X
1
1
D4
0
MOUTEN
X
X
1
1
GPIOPL
D3
Speaker
Enabled
SMPLR[2:0]
Yes
Yes
No
No
D2
MONO output
GPIOSEL[2:0]
Enabled
Yes
Yes
No
No
D1
NAU8812
January 2011
SCLKEN 0x000
D0
Default
0x000