NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 60

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Before the device is functional or any of the individual analog blocks are enabled REFIMP[1:0] address (0x01) and
ABIASEN[3] address (0x01) must be set. The REFIMP[1:0] bits control the resistor values (“R” in Figure3) that
generates the mid supply reference, VREF. REFIMP[1:0] bits control the power up ramp rate in conjunction with the
external decoupling capacitor. A small value of “R” allows fast ramp up of the mid supply reference and a large value
of “R” provides higher PSRR of the mid supply reference.
The master analog biasing of the device is enabled by setting ABIASEN[3] address (0x01). This bit has to be set
before for the device to function.
Saving power is one of the critical features in a semiconductor device specially ones used in the Bluetooth headsets
and handheld device. NAU8812 has two oversampling rates 64x and 128x. The default mode of operation for the
DAC and ADC is in 64x oversampling mode which is set by programming DACOS[3] address (0x0A) and ADCOS[3]
address (0x0E) respectively to LOW. Power is saved by choosing 64x oversampling rate compared to 128x
emPowerAudio
Datasheet Revision 2.0
12.11.5.
12.11.6.
™
Reference Impedance (REFIMP) and Analog Bias
Power Saving
Output stages
Un-mute DAC
Name
Un-mute DAC
Power Management
Output stages
Power supplies
MOUTMXEN[3]
MOUTEN[7]
NSPKEN[6]
PSPKEN[5]
DACMT[6] = 0
VDDSPK - 3.3V operation
Name
Table 31: Power down Sequence
Table 30: Power up sequence
Page 60 of 109
DACMT[6] = 1
PWRM1 = 0x000
MOUTEN[7]
NSPKEN[6]
PSPKEN[5]
Analog – VDDA
Buffer - VDDB
Digital – VDDC
Output driver – VDDSPK
Power Down Both Cases
Power Up
MOUTMXEN[3]
MOUTEN[7]
NSPKEN[6]
PSPKEN[5]
DACMT[6] = 0
VDDSPK - 5.0V operation
NAU8812
January 2011