NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 88

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Location
emPowerAudio
Datasheet Revision 2.0
Bit
0x49
Addr
0
1
2
3
4
5
8
13.15.
SPIEN
Set DAC to use 256x
oversampling rate
Enable control to use PLL
output when PLL is not in
phase locked condition
Enable control to mute
DAC limiter output when
softmute is enabled
Enable control to delay use
of notch filter output when
filter is enabled
Enable control for short
frame cycle detection logic
Enable DSP state flush on
short frame sync event
Set SPI control bus mode
regardless of state of Mode
pin
D8
MISC CONTROL REGISTER
™
Bit Description
FSERRVAL[1:0] FSERFLSH FSERRENA NFDLY DACINMT PLLLOCKP DACOS256 0x000
D7
MODE
Pin
0
1
x
B1
0
0
1
1
D6
SPIEN[8]
Bit
0
0
1
B0
DACOS256
PLLLOCKP
DACINMT
NFDLY
FSERRENA
FSERFLSH
SPIEN
0
1
0
1
Bit Name
D5
Address
Page 88 of 109
0x49
Short frame sync detection period value
Use oversampling rate as
determined by Register 0x0A[3]
(default)
PLL VCO output disabled when
PLL is in unlocked condition
(default)
DAC limiter output may not
move to exactly zero during
Softmute (default)
Delay using notch filter output
512 sample times after notch
enabled (default)
Short frame cycle detection
logic enabled
Ignore short frame sync events
(default)
Default Operation
trigger if frame time less than
D4
2-Wire Interface (Write/Read)
SPI Interface 16-bit (Write ONLY)
SPI Interface 32-bit (Read)
SPI Interface 24-bit (Write)
(SSOP 28-Pin Write ONLY,
QFN 32-Pin Write/Read)
255 MCLK edges
253 MCLK edges
254 MCLK edges
255 MCLK edges
FSERRVAL[1:0]
D3
0
Description
D2
Bit Value
D1
Set DAC to 256x
oversampling rate regardless
of Register 0x0A[3]
PLL VCO output used as-is
when PLL is in unlocked
condition
DAC limiter output muted to
exactly zero during Softmute
Use notch filter output
immediately after notch filter
is enabled
Short frame cycle detection
logic disabled
Set DSP state to initial
conditions on short frame
sync event
Force SPI 4-wire mode
regardless of state of Mode
pin
NAU8812
January 2011
D0
1
Default