NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 59

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Although it is not required, it is strongly recommended that a Software Reset command should be issued after power-
on and after the power-on-reset condition is ended. This will help insure reliable operation under every power
sequencing condition that could occur.
The control registers can be reset to default conditions by writing any value to RST address (0x00), using any of the
control interface modes. Writing valid data to any other register disables the reset, but all registers will need to be
initiated again appropriate to the operation. See the applications section on powering NAU8812 up for information on
avoiding pops and clicks after a software reset.
Most audio products have issues during power up and power down in the form of pop and click noise. To avoid cuch
issues the NAU8812 provides four different power supplies VDDA, VDDB, VDDC and VDDSPK with separated
grounds VSSA, VSSD and VSSSPK. The audio CODEC circuitry, the input amplifiers, output amplifiers and drivers,
the audio ADC and DAC converters, the PLL, and so on, can be powered up and down individually by software
control via 2-Wire or SPI interface. The zero cross function should be used when changing the volume in the PGAs
to avoid any audible pops or clicks.
recommended power-up and power-down sequences for both the modes are outlined as following.
emPowerAudio
Datasheet Revision 2.0
12.11.3. Software Reset
12.11.4. Power Up/Down Sequencing
™
Power supplies
Mode
Power
Management
Clock divider
PLL
DAC, ADC
Mixers
Name
Analog – VDDA
Buffer - VDDB
Digital – VDDC
Output driver - VDDSPK
SPKBST[2] = 0
MOUTBST[3] = 0
REFIMP[1:0]
as required (value of the REFIMP bits based on the startup time
which is a combination of the reference impedance and the
decoupling capacitor on VREF)
ABIASEN[3] = 1
(enables the internal device bias for all analog blocks)
IOBUFEN[2] = 1
(enables the internal device bias buffer)
CLKIOEN[0] if required
BCLKSEL[4:2] if required
MCLKSEL[7:5] if required
PLLEN[5] if required
DACEN[0] = 1
ADCEN[0] = 1
SPKMXEN[2]
VDDSPK - 3.3V operation
There are two different modes of operation 5.0V and 3.3V mode.
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Power Up
Analog – VDDA
Buffer - VDDB
Digital – VDDC
Output driver – VDDSPK
SPKBST[2] = 1
MOUTBST[3] = 1
CLKIOEN[0] if required
BCLKSEL[4:2] if required
MCLKSEL[7:5] if required
PLLEN[5] if required
DACEN[0] = 1
ADCEN[0] = 1
SPKMXEN[2]
VDDSPK - 5.0V operation
NAU8812
January 2011
The