NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 43

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In Master Mode, the IMCLK signal is used to generate FS and BCLK signals that are driven onto the FS and BCLK
pins and input to the Digital Audio Interface. FS is always IMCLK/256 and the duty cycle of FS is automatically
adjusted to be correct for the mode selected in the Digital Audio Interface. The frequency of BCLK may optionally be
divided to optimize the bit clock rate for the application scenario.
In Slave Mode, there is no connection between IMCLK and the FS and BCLK pins. In this mode, FS and BLCK are
strictly input pins, and it is the responsibility of the system designer to insure that FS, BCLK, and IMCLK are
synchronous and scaled appropriately for the application.
The PLL may be optionally used to multiply an external input clock reference frequency by a high resolution fractional
number. To enable the use of the widest possible range of external reference clocks, the PLL block includes an
optional divide-by-two prescaler for the input clock, a fixed divide-by-four scaler on the PLL output, and an additional
programmable integer divider that is the Master Clock Prescaler.
The high resolution fraction for the PLL is the ratio of the desired PLL oscillator frequency (f
frequency at the PLL input (f
xy.abcdefgh.
portion, “abcdefgh”. The fractional portion of the multiplier is a value that when represented as a 24-bit binary
number (stored in three 9-bit registers on the NAU8812), very closely matches the exact desired multiplier factor.
To keep the PLL within its optimal operating range, the integer portion of the decimal number (“xy”), must be any of
the following decimal values: 6, 7, 8, 9, 10, 11, or 12. The input and output dividers outside of the PLL are often
helpful to scale frequencies as needed to keep the “xy” value within the required range. Also, the optimum PLL
oscillator frequency is in the range between 90MHz and 100MHz, and thus, it is best to keep f
emPowerAudio
Datasheet Revision 2.0
0x01
0x06
0x07
0x24
0x25
0x26
0x27
Addr
12.8.1. Phase Locked Loop (PLL) General description
DCBUFEN
CLKM
D8
™
0
0
0
To program the NAU8812, this value is separated into an integer portion (“xy”), and a fractional
D7
0
0
0
0
MCLKSEL[2:0]
1
). This can be represented as R = f
AUXEN
D6
0
0
0
Table 23: Registers associated with PLL
PLLEN
D5
0
0
Page 43 of 109
PLLK[17:9]
MICBIASEN
PLLK[8:0]
PLLMCLK
D4
0
BCLKSEL[2:0]
ABIASEN IOBUFEN
PLLK[23:18]
2
D3
/f
1
, with R in the form of a decimal number:
SMPLR[2:0]
D2
PLLN[3:0]
D1
0
2
REFIMP
within this range.
NAU8812
2
January 2011
), and the reference
CLKIOEN
SCLKEN
D0
Default
0x00C
0x140
0x000
0x008
0x093
0x0E9