NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 42

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The NAU8812 has two basic clock modes that support the ADC and DAC data converters. It can accept external
clocks in the slave mode, or in the master mode, it can generate the required clocks from an external reference
frequency using an internal PLL (Phase Locked Loop). The internal PLL is a fractional type scaling PLL, and
therefore, a very wide range of external reference frequencies can be used to create accurate audio sample rates.
Separate from this ADC and DAC clock subsystem, audio data are clocked to and from the NAU8812 by means of
the control logic described in the Digital Audio Interfaces section. The Frame Sync (FS) and Bit Clock (BCLK) pins in
the Digital Audio Interface manage the audio bit rate and audio sample rate for this data flow.
It is important to understand that the Digital Audio Interface does not determine the sampling rate for the ADC and
DAC data converters, and instead, this rate is derived exclusively from the Internal Master Clock (IMCLK). It is
therefore a requirement that the Digital Audio Interface and data converters be operated synchronously, and that the
FS, BCLK, and IMCLK signals are all derived from a common reference frequency. If these three clocks signals are
not synchronous, audio quality will be reduced.
The IMCLK is always exactly 256 times the sampling rate of the data converters. IMCLK is output from the Master
Clock Prescaler. The prescaler reduces by an integer division factor the input frequency input clock. The source of
this input frequency clock is either the external MCLK pin, or the output from the internal PLL Block.
emPowerAudio
Datasheet Revision 2.0
12.8.
GPIO1
MCLK
/CSb
CLOCK GENERATION BLOCK
™
f/2
GPIO1SEL[2:0]
(0x08)
PLLMCLK[4]
(0x24)
…
f
PLL BLOCK
1
R=f
PLL1
Figure 21: PLL and Clock Select Circuit
2
/f
1
f
GPIO1PLL[5:4]
2
(0x08)
f/N
Page 42 of 109
f/4
f
PLL
CLKM[8]
(0x06)
Digital Audio
Interface
MCLKSEL[7:5]
(0x06)
BCLKSEL[4:2]
f/N
(0x06)
CLKIOEN[0]
(0x06)
IMCLK
IMCLK/
N
ADCOS[3]
DACOS[3]
(0x0E)
(0x0A)
f/N
f/N
IMCLK/
256
NAU8812
January 2011
DAC
ADC
BCLK
FS