NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 9

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NAU8812
List of Figures
7.
Figure 1: 28-Pin SSOP Package ................................................................................................................................... 2
Figure 2: 32-Pin QFN Package ..................................................................................................................................... 2
Figure 3: NAU8812 General Block Diagram ................................................................................................................. 4
Figure 4: Auxiliary Input Circuit Block Diagram with AUXM[3] = 0 .............................................................................. 17
Figure 5: Auxiliary Input Circuit Block Diagram with AUXM[3] = 1 .............................................................................. 17
Figure 6: Input PGA Circuit Block Diagram ................................................................................................................. 18
Figure 7: Boost Stage Block Diagram ......................................................................................................................... 20
Figure 8: Microphone Bias Schematic ......................................................................................................................... 22
Figure 9: ADC Digital Filter Path Block Diagram ......................................................................................................... 24
Figure 10: ALC Block Diagram .................................................................................................................................... 27
Figure 11: ALC Response Graph ................................................................................................................................ 27
Figure 12: ALC Normal Mode Operation ..................................................................................................................... 29
Figure 13: ALC Hold Time ........................................................................................................................................... 30
Figure 14: ALC Limiter Mode Operations .................................................................................................................... 30
Figure 15: ALC Operation with Noise Gate disabled ................................................................................................... 31
Figure 16: ALC Operation with Noise Gate Enabled ................................................................................................... 32
Figure 17: DAC Digital Filter Path ............................................................................................................................... 33
Figure 18: DAC Digital Limiter Control ........................................................................................................................ 35
Figure 19: Speaker and MONO Analogue Outputs ..................................................................................................... 36
Figure 20: Tie-off Options for the Speaker and MONO output Pins ............................................................................ 38
Figure 21: PLL and Clock Select Circuit ...................................................................................................................... 42
Figure 22: Register write operation using a 16-bit SPI Interface ................................................................................. 47
Figure 23: Register Write operation using a 24-bit SPI Interface ................................................................................ 48
Figure 24: Register Read operation through a 32-bit SPI Interface ............................................................................ 48
Figure 25: Valid START Condition .............................................................................................................................. 49
Figure 26: Valid Acknowledge ..................................................................................................................................... 49
Figure 27: Valid STOP Condition ................................................................................................................................ 49
Figure 28: Slave Address Byte, Control Address Byte, and Data Byte ....................................................................... 49
Figure 29: Byte Write Sequence ................................................................................................................................. 50
Figure 30: 2-Wire Read Sequence .............................................................................................................................. 50
Figure 31: Right Justified Audio Interface (Normal Mode) ........................................................................................... 52
Figure 32: Right Justified Audio Interface (Special mode) .......................................................................................... 52
Figure 33: Left Justified Audio Interface (Normal Mode) ............................................................................................. 53
Figure 34: Left Justified Audio Interface (Special mode) ............................................................................................. 53
Figure 35: I2S Audio Interface (Normal Mode) ............................................................................................................ 54
Figure 36: I2S Audio Interface (Special mode)............................................................................................................ 54
emPowerAudio
™
Datasheet Revision 2.0
Page 9 of 109
January 2011