YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet
YLCDRSK2378
Specifications of YLCDRSK2378
Related parts for YLCDRSK2378
YLCDRSK2378 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2378, 16 H8S/2378R Group Hardware Manual Renesas ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition (only for revised versions) The list of revisions ...
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The H8S/2378 Group and H8S/2378R Group microcomputers (MCU) made up of the H8S/2000 CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen ...
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In order to understand the details of the CPU’s functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. For the execution state of each instruction in this LSI, see Appendix D, Bus State during Execution of Instructions. In order to ...
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Main Revisions for This Edition Item Page 3.4 Memory Map in 79 Each Operating Mode Figure 3.2 Memory Map for H8S/2378 and H8S/2378R (2) Figure 3.7 Memory 84 Map for H8S/2374 and H8S/2374R (1) Figure 3.15 Memory 92 Map for ...
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Item Page Section 8 EXDMA 359 Controller (EXDMAC) 8.3.5 EXDMA 370 Address Control Register (EDACR) 372 8.4.2 Address Modes 376 Single Address Mode: Rev.7.00 Mar. 18, 2009 page viii of lxvi REJ09B0109-0700 Revision (See Manual for Details) Description amended … ...
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Item Page 8.4.2 Address Modes 377 Figure 8.3 Data Flow in Single Address Mode Figure 8.4 Example of 378 Timing in Single Address Mode Revision (See Manual for Details) Figure amended External device with DACK Figure amended Transfer from external ...
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Item Page 9.8.5 Chain Transfer 453 10.1.4 Pin Functions 471 • P10/PO8/TIOCA0 10.9.7 Pin Functions 511 • PA7/A23/IRQ7, PA6/A22/IRQ6, PA5/A21/IRQ5 • PA4/A20/IRQ4 511 • PA3/A19, PA2/A18, 512 PA1/A17, PA20/A16 10.10.5 Pin Functions 515 10.11.5 Pin Functions 519 Rev.7.00 Mar. 18, ...
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Item Page 10.12.5 Pin Functions 523 10.13.5 Pin Functions 527 10.14.4 Pin Functions 531 • PF7/φ 10.16.1 Port H Data 541 Direction Register (PHDDR) 15.3.7 Serial Status 705 Register (SSR) Normal Serial Communication Interface Mode (When SMIF in SCMR is ...
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Item Page 15.3.9 Bit Rate 712 Register (BRR) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 713 713 714 Rev.7.00 Mar. 18, 2009 page xii of lxvi REJ09B0109-0700 Revision (See Manual for Details) Table amended Operating Frequency φ ...
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Item Page 15.4.4 SCI 727 Initialization (Asynchronous Mode) 15.6.2 SCI 741 Initialization (Clocked Synchronous Mode) 2 Section Bus 771 Interface 2 (IIC2) (Option) 2 16.3 Bus Control 776 Register A (ICCRA) Table 16.2 Transfer Rate ...
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Item Page 16.3.5 I2C Bus Status 782 Register (ICSR) 783 16.4.7 Example of 797 Use Figure 16.14 Sample Flowchart for Master Transmit Mode Rev.7.00 Mar. 18, 2009 page xiv of lxvi REJ09B0109-0700 Revision (See Manual for Details) Table amended Bit ...
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Item Page 16.4.7 Example of 798 Use Figure 16.15 Sample Flowchart for Master Receive Mode Figure 16.17 Sample 800 Flowchart for Slave Receive Mode 16.7 Usage Notes 803 2 ( bus interface 2 (IIC2) master receive mode (4) ...
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Item Page 17.1 Features 806 Figure 17.1 Block Diagram of A/D Converter 21.1 Features 862 21.1.1 Operating 864 Mode 21.3.1 Programming/ 872 Erasing Interface Register 21.3.2 Programming/ 879 Erasing Interface Parameter 21.3.3 Flash Vector 889 Address Control Register (FVACR) Rev.7.00 ...
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Item Page 21.4.2 User Program 889 Mode (2) Programming Procedure in User Program Mode 6. The FPEFEQ and FUBRA parameters are set for initialization. 21.8 Serial 930 Communication Interface Specification for Boot Mode (4) Inquiry and Selection States (b) Device ...
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Item Page 26.1.2 DC 1020 Characteristics Table 26.2 DC Characteristics (1) Table 26.4 1022 Permissible Output Currents 26.1.6 Flash Memory 1033 Characteristics Table 26.13 Flash Memory Characteristics (0.35-μm F-ZTAT Version) 1034 Rev.7.00 Mar. 18, 2009 page xviii of lxvi REJ09B0109-0700 ...
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Item Page 26.2.2 DC 1036 Characteristics Table 26.15 DC Characteristics Table 26.17 1038 Permissible Output Currents 26.2.3 AC 1044 Characteristics Table 26.21 Bus Timing (2) Revision (See Manual for Details) Table amended Item Symbol Min. STBY, Input high V V ...
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Item Page 26.3.2 DC 1051 Characteristics Table 26.28 DC Characteristics Table 26.30 1053 Permissible Output Currents 26.3.3 AC 1059 Characteristics Table 26.34 Bus Timing (2) 26.4.3 Bus Timing 1070 Figure 26.7 Basic Bus Timing: Two-State Access Figure 26.8 Basic Bus ...
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Item Page 26.4.3 Bus Timing 1074 Figure 26.11 Basic Bus Timing: Three- State Access (CS Assertion Period Extended) Figure 26.14 DRAM 1077 Access Timing: Two- State Access Figure 26.15 DRAM 1078 Access Timing: Two- State Access, One Wait Figure 26.16 ...
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Item Page 26.4.4 DMAC and 1090 EXDMAC Timing Figure 26.30 DMAC and EXDMAC TEND/ETEND Output Timing Figure 26.31 DMAC 1090 and EXDMAC DREQ/EDREQ Input Timing Figure 26.32 1090 EXDMAC EDRAK Output Timing C. Package 1107 Dimensions Figure C.2 Package Dimensions ...
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Section 1 Overview................................................................................................1 1.1 Features .................................................................................................................................. 1 1.2 Block Diagram ....................................................................................................................... 3 1.3 Pin Description....................................................................................................................... 7 1.3.1 Pin Arrangement ....................................................................................................... 7 1.3.2 Pin Arrangement in Each Operating Mode ............................................................. 12 1.3.3 Pin Functions .......................................................................................................... 18 Section 2 CPU......................................................................................................35 2.1 Features ...
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Effective Address Calculation ................................................................................ 66 2.8 Processing States.................................................................................................................. 68 2.9 Usage Note........................................................................................................................... 69 2.9.1 Note on Bit Manipulation Instructions.................................................................... 69 Section 3 MCU Operating Modes ....................................................................... 71 3.1 Operating Mode Selection.................................................................................................... 71 3.2 Register Descriptions ........................................................................................................... 72 3.2.1 Mode ...
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IRQ Status Register (ISR)..................................................................................... 116 5.3.6 IRQ Pin Select Register (ITSR) ............................................................................ 117 5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 119 5.4 Interrupt Sources ................................................................................................................ 120 5.4.1 External Interrupts ................................................................................................ 120 5.4.2 Internal Interrupts.................................................................................................. 121 5.5 Interrupt ...
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Bus Specifications................................................................................................. 172 6.4.3 Memory Interfaces ................................................................................................ 174 6.4.4 Chip Select Signals ............................................................................................... 175 6.5 Basic Bus Interface ............................................................................................................ 176 6.5.1 Data Size and Data Alignment.............................................................................. 176 6.5.2 Valid Strobes......................................................................................................... 178 6.5.3 Basic Timing......................................................................................................... 178 6.5.4 Wait Control ......................................................................................................... ...
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Burst ROM Interface.......................................................................................................... 246 6.8.1 Basic Timing......................................................................................................... 246 6.8.2 Wait Control ......................................................................................................... 248 6.8.3 Write Access ......................................................................................................... 248 6.9 Idle Cycle ........................................................................................................................... 249 6.9.1 Operation .............................................................................................................. 249 6.9.2 Pin States in Idle Cycle ......................................................................................... 268 6.10 Write Data Buffer ...
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Idle Mode.............................................................................................................. 314 7.5.4 Repeat Mode ......................................................................................................... 316 7.5.5 Single Address Mode............................................................................................ 320 7.5.6 Normal Mode........................................................................................................ 323 7.5.7 Block Transfer Mode ............................................................................................ 326 7.5.8 Basic Bus Cycles................................................................................................... 331 7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles ................................................ 332 7.5.10 ...
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Repeat Area Function ........................................................................................... 383 8.4.7 Registers during DMA Transfer Operation........................................................... 385 8.4.8 Channel Priority Order.......................................................................................... 390 8.4.9 EXDMAC Bus Cycles (Dual Address Mode)....................................................... 393 8.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 400 8.4.11 Examples of Operation Timing ...
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Examples of Use of the DTC ............................................................................................. 448 9.7.1 Normal Mode........................................................................................................ 448 9.7.2 Chain Transfer ...................................................................................................... 449 9.7.3 Chain Transfer when Counter = 0......................................................................... 450 9.7.4 Software Activation .............................................................................................. 452 9.8 Usage Notes ....................................................................................................................... 452 9.8.1 Module Stop Mode ...
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Port 6 Register (PORT6)....................................................................................... 495 10.6.4 Pin Functions ........................................................................................................ 496 10.7 Port 8.................................................................................................................................. 499 10.7.1 Port 8 Data Direction Register (P8DDR).............................................................. 499 10.7.2 Port 8 Data Register (P8DR)................................................................................. 500 10.7.3 Port 8 Register (PORT8)....................................................................................... 500 10.7.4 Pin Functions ........................................................................................................ ...
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Port E Data Direction Register (PEDDR) ............................................................. 525 10.13.2 Port E Data Register (PEDR)................................................................................ 526 10.13.3 Port E Register (PORTE)...................................................................................... 526 10.13.4 Port E Pull-up Control Register (PEPCR) ............................................................ 527 10.13.5 Pin Functions ........................................................................................................ 527 10.13.6 Port E Input ...
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PWM Modes ......................................................................................................... 598 11.4.6 Phase Counting Mode ........................................................................................... 603 11.5 Interrupt Sources ................................................................................................................ 609 11.6 DTC Activation.................................................................................................................. 611 11.7 DMAC Activation.............................................................................................................. 611 11.8 A/D Converter Activation .................................................................................................. 611 11.9 Operation Timing............................................................................................................... 612 11.9.1 Input/Output Timing ............................................................................................. 612 11.9.2 ...
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Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) .......................................................... 648 12.4.7 Inverted Pulse Output ........................................................................................... 650 12.4.8 Pulse Output Triggered by Input Capture ............................................................. 651 12.5 Usage Notes ....................................................................................................................... 651 12.5.1 Module Stop Mode Setting ................................................................................... ...
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Section 14 Watchdog Timer (WDT)..................................................................677 14.1 Features .............................................................................................................................. 677 14.2 Input/Output Pin................................................................................................................. 678 14.3 Register Descriptions ......................................................................................................... 679 14.3.1 Timer Counter (TCNT)......................................................................................... 679 14.3.2 Timer Control/Status Register (TCSR) ................................................................. 679 14.3.3 Reset Control/Status Register (RSTCSR) ............................................................. 681 14.4 Operation............................................................................................................................ 682 ...
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Serial Data Reception (Asynchronous Mode)....................................................... 730 15.5 Multiprocessor Communication Function.......................................................................... 734 15.5.1 Multiprocessor Serial Data Transmission ............................................................. 735 15.5.2 Multiprocessor Serial Data Reception .................................................................. 737 15.6 Operation in Clocked Synchronous Mode ......................................................................... 740 15.6.1 Clock..................................................................................................................... 740 15.6.2 SCI Initialization ...
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I C Bus Interrupt Enable Register (ICIER)........................................................... 780 2 16.3 Bus Status Register (ICSR) ............................................................................ 782 16.3.6 Slave address register (SAR) ................................................................................ 784 2 16.3 Bus Transmit Data Register (ICDRT) ............................................................ 785 2 16.3.8 ...
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Section 18 D/A Converter ................................................................................. 821 18.1 Features .............................................................................................................................. 821 18.2 Input/Output Pins ............................................................................................................... 824 18.3 Register Descriptions ......................................................................................................... 825 18.3.1 D/A Data Registers (DADR0 to DADR5) .................................................. 825 18.3.2 D/A Control Registers 01, 23, and 45 ...
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Operating Mode .................................................................................................... 864 21.1.2 Mode Comparison................................................................................................. 865 21.1.3 Flash MAT Configuration..................................................................................... 866 21.1.4 Block Division ...................................................................................................... 867 21.1.5 Programming/Erasing Interface ............................................................................ 868 21.2 Input/Output Pins ............................................................................................................... 870 21.3 Register Descriptions ......................................................................................................... 871 21.3.1 Programming/Erasing Interface Register .............................................................. 872 ...
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Section 24 Power-Down Modes ........................................................................ 965 24.1 Register Descriptions ......................................................................................................... 968 24.1.1 Standby Control Register (SBYCR) ..................................................................... 968 24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)..................... 970 24.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) ...
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AC Characteristics .............................................................................................. 1039 26.2.4 A/D Conversion Characteristics.......................................................................... 1048 26.2.5 D/A Conversion Characteristics.......................................................................... 1048 26.2.6 Flash Memory Characteristics ............................................................................ 1049 26.3 Electrical Characteristics for H8S/2374, H8S/2372, H8S/2371, H8S/2370, H8S/2378R, H8S/2374R, H8S/2372R, H8S/2371R, H8S/2370R.................................... 1050 26.3.1 Absolute Maximum Ratings ............................................................................... ...
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Rev.7.00 Mar. 18, 2009 page xlii of lxvi REJ09B0109-0700 ...
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Section 1 Overview................................................................................................1 Figure 1.1 Internal Block Diagram for H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group .................................................................... 3 Figure 1.2 Internal Block Diagram for H8S/2377 and H8S/2377R.............................................. 4 Figure 1.3 Internal Block Diagram for H8S/2375 and H8S/2375R.............................................. 5 ...
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Figure 3.9 Memory Map for H8S/2373 and H8S/2373R............................................................ 86 Figure 3.10 Memory Map for H8S/2372 and H8S/2372R (1) ...................................................... 87 Figure 3.11 Memory Map for H8S/2372 and H8S/2372R (2) ...................................................... 88 Figure 3.12 Memory Map for H8S/2371 and H8S/2371R (1) ...
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Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) ............ 185 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 186 Figure 6.18 Example of Wait State Insertion Timing................................................................. 188 Figure 6.19 Example ...
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Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled (SDWCD = 1) ......................................................................................................... 227 Figure 6.49 DQMU and DQML Control Timing (Upper Byte Write Access: SDWCD = 0, CAS Latency 2) ................................................................................ 228 Figure 6.50 ...
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Figure 6.76 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) .......... 259 Figure 6.77 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC ...
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Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) .......................... 335 Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer................. 336 Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer..... 337 ...
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Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer............................. 395 Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge ......... 396 Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling ...
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Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) .............. 413 Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) ..................... 414 Figure 8.42 External Request/Cycle ...
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Figure 11.11 Example of Synchronous Operation........................................................................ 591 Figure 11.12 Compare Match Buffer Operation........................................................................... 592 Figure 11.13 Input Capture Buffer Operation............................................................................... 592 Figure 11.14 Example of Buffer Operation Setting Procedure..................................................... 593 Figure 11.15 Example of Buffer Operation (1) ............................................................................ 594 Figure ...
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Figure 11.52 Contention between Overflow and Counter Clearing ............................................. 627 Figure 11.53 Contention between TCNT Write and Overflow..................................................... 628 Section 12 Programmable Pulse Generator (PPG) ............................................ 631 Figure 12.1 Block Diagram of PPG............................................................................................ 632 Figure 12.2 Overview Diagram of PPG...................................................................................... ...
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Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 723 Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 725 Figure 15.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode). 726 ...
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Figure 15.35 Example of Synchronous Transmission Using DTC............................................... 766 Figure 15.36 Sample Flowchart for Mode Transition during Transmission................................. 768 Figure 15.37 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission) ........................................................ 769 Figure 15.38 Port Pin States during Mode ...
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Figure 18.2 Block Diagram of D/A Converter for H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R ....................................................................................................... 823 Figure 18.3 Example of D/A Converter Operation..................................................................... 830 Section 20 Flash Memory (0.35-μm F-ZTAT Version) ....................................833 Figure 20.1 Block Diagram of Flash Memory........................................................................... 834 Figure ...
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Section 22 Masked ROM .................................................................................. 953 Figure 22.1 Block Diagram of 256-kbyte Masked ROM (HD6432375) .................................... 953 Section 23 Clock Pulse Generator ..................................................................... 955 Figure 23.1 Block Diagram of Clock Pulse Generator ............................................................... 955 Figure 23.2 Connection of Crystal Resonator ...
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Figure 26.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1)............. 1083 Figure 26.23 External Bus Release Timing ................................................................................ 1084 Figure 26.24 External Bus Request Output Timing.................................................................... 1084 Figure 26.25 Synchronous DRAM Basic Access Timing (CAS Latency 2) .............................. ...
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Rev.7.00 Mar. 18, 2009 page lviii of lxvi REJ09B0109-0700 ...
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Section 1 Overview................................................................................................1 Table 1.1 Pin Arrangement in Each Operating Mode ............................................................... 12 Table 1.2 Pin Functions............................................................................................................. 18 Section 2 CPU......................................................................................................35 Table 2.1 Instruction Classification........................................................................................... 51 Table 2.2 Operation Notation .................................................................................................... 52 Table 2.3 Data Transfer Instructions ......................................................................................... 53 Table ...
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Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ......................................... 173 Table 6.3 Data Buses Used and Valid Strobes ........................................................................ 178 Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space.............. 191 Table 6.5 Relation between ...
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Table 9.6 Register Function in Block Transfer Mode ............................................................. 442 Table 9.7 DTC Execution Status ............................................................................................. 446 Table 9.8 Number of States Required for Each Execution Status ........................................... 446 Section 10 I/O Ports ...........................................................................................455 Table 10.1 Port Functions ......................................................................................................... 456 ...
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Table 11.29 Cascaded Combinations .......................................................................................... 596 Table 11.30 PWM Output Registers and Output Pins................................................................. 599 Table 11.31 Clock Input Pins in Phase Counting Mode.............................................................. 603 Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1 ........................................ 604 Table 11.33 Up/Down-Count Conditions ...
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Section Bus Interface 2 (IIC2) (Option) .................................................771 Table 16.1 Pin Configuration .................................................................................................... 773 Table 16.2 Transfer Rate ........................................................................................................... 776 Table 16.3 Interrupt Requests ................................................................................................... 801 Table 16.4 Time for monitoring SCL........................................................................................ 802 Section 17 A/D Converter..................................................................................805 ...
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Table 21.8 (2) Useable Area for Erasure in User Program Mode................................................. 914 Table 21.8 (3) Useable Area for Programming in User Boot Mode ............................................. 916 Table 21.8 (4) Useable Area for Erasure in User Boot Mode....................................................... 918 Table 21.9 Hardware ...
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Table 26.20 Bus Timing (1) ...................................................................................................... 1041 Table 26.21 Bus Timing (2) ...................................................................................................... 1043 Table 26.22 DMAC and EXDMAC Timing ............................................................................. 1045 Table 26.23 Timing of On-Chip Peripheral Modules................................................................ 1046 Table 26.24 A/D Conversion Characteristics ............................................................................ 1048 Table 26.25 D/A ...
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Rev.7.00 Mar. 18, 2009 page lxvi of lxvi REJ09B0109-0700 ...
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Features • High-speed H8S/2000 CPU with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions • Various peripheral functions DMA controller (DMAC) EXDMA controller (EXDMAC) * Data ...
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Section 1 Overview • On-chip memory ROM Type Model Flash memory version HD64F2378B HD64F2378R HD64F2377 HD64F2377R HD64F2374 HD64F2374R HD64F2372 HD64F2372R HD64F2371 HD64F2371R HD64F2370 HD64F2370R Masked ROM version HD6432375 HD6432375R ROMless version HD6412373 HD6412373R • General I/O ports I/O pins: 96 ...
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Block Diagram MD2 MD1 MD0 DCTL EXTAL XTAL EMLE STBY RES WDTOVF NMI PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR * PF2/LCAS/IRQ15/DQML * PF1/UCAS/IRQ14/DQMU PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO * PG3/CS3/RAS3/CAS PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P85/(IRQ5)/SCK3/EDACK3 P84/(IRQ4)/EDACK2 ...
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Section 1 Overview MD2 MD1 MD0 DCTL EXTAL XTAL EMLE STBY RES WDTOVF NMI PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR * PF2/LCAS/IRQ15/DQML * PF1/UCAS/IRQ14/DQMU PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO * PG3/CS3/RAS3/CAS PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P85/(IRQ5)/SCK3/EDACK3 P84/(IRQ4)/EDACK2 ...
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MD2 MD1 MD0 DCTL EXTAL XTAL EMLE STBY RES WDTOVF NMI PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR * PF2/LCAS/IRQ15/DQML * PF1/UCAS/IRQ14/DQMU PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO * PG3/CS3/RAS3/CAS PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P85/(IRQ5)/SCK3 P84/(IRQ4) P83/(IRQ3)/RxD3 P82/(IRQ2) P81/(IRQ1)/TxD3 ...
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Section 1 Overview MD2 MD1 MD0 DCTL EXTAL XTAL EMLE STBY RES WDTOVF NMI PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR * PF2/LCAS/IRQ15/DQML * PF1/UCAS/IRQ14/DQMU PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO * PG3/CS3/RAS3/CAS PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P85/(IRQ5)/SCK3 P84/(IRQ4) ...
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Pin Description 1.3.1 Pin Arrangement PG2/CS2/RAS2/RAS 109 PG3/CS3/RAS3/CAS * 1 110 AVcc 111 Vref 112 P40/AN0 113 P41/AN1 114 P42/AN2 115 P43/AN3 116 P44/AN4 117 P45/AN5 118 P46/AN6/DA0 119 P47/AN7/DA1 120 P90/AN8 121 P91/AN9 122 P92/AN10 123 P93/AN11 124 ...
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Section 1 Overview PG2/CS2/RAS2/RAS 109 PG3/CS3/RAS3/CAS * 1 110 AVcc 111 Vref 112 P40/AN0 113 P41/AN1 114 P42/AN2 115 P43/AN3 116 P44/AN4 117 P45/AN5 118 P46/AN6/DA0 119 P47/AN7/DA1 120 P90/AN8 121 P91/AN9 122 P92/AN10 123 P93/AN11 124 P94/AN12/DA2 125 P95/AN13/DA3 ...
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PG2/CS2/RAS2/RAS PG3/CS3/RAS3/CAS * 109 1 110 AVcc 111 Vref 112 P40/AN0 113 P41/AN1 114 P42/AN2 115 P43/AN3 116 P44/AN4 117 P45/AN5 118 P46/AN6 119 P47/AN7 120 P90/AN8 121 P91/AN9 122 P92/AN10 123 P93/AN11 124 P94/AN12/DA2 125 P95/AN13/DA3 126 P96/AN14 127 ...
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Section 1 Overview PG2/CS2/RAS2/RAS 109 PG3/CS3/RAS3/CAS * 1 110 AVcc 111 Vref 112 P40/AN0 113 P41/AN1 114 P42/AN2 115 P43/AN3 116 P44/AN4 117 P45/AN5 118 P46/AN6 119 P47/AN7 120 P90/AN8 121 P91/AN9 122 P92/AN10 123 P93/AN11 124 P94/AN12/DA2 125 P95/AN13/DA3 ...
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A VSS MD1 MD0 P32 B MD2 VCC P31 P34 C PC0 P80 PC1 P30 D PC4 PC2 PC3 P53 E PC7 VSS PC5 PB0 F PB3 PC6 PB1 VSS G PB6 PB2 PA0 PB4 H ...
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Section 1 Overview 1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin No. LQFP- LGA- 144 145 Mode Mode MD2 MD2 2 A1 Vss Vss 3 ...
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Pin No. LQFP- LGA- 144 145 Mode Mode 2 * A20/IRQ4 * 5 A20/IRQ4 * PA5/A21/IRQ5 PA5/A21/IRQ5 30 K2 PA6/A22/IRQ6 PA6/A22/IRQ6 31 J3 PA7/A23/IRQ7 PA7/A23/IRQ7 32 K1 EMLE EMLE 33 L2 P81/(IRQ1)/ P81/(IRQ1)/ ...
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Section 1 Overview Pin No. LQFP- LGA- 144 145 Mode Mode P17/PO15/ P17/PO15/ TIOCB2/TCLKD/ TIOCB2/TCLKD/ EDRAK3 * EDRAK3 * Vss Vss 51 L6 P20/PO0/ P20/PO0/ TIOCA3/(IRQ8) TIOCA3/(IRQ8 P21/PO1/ ...
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Pin No. LQFP- LGA- 144 145 Mode Mode M11 D6 PE6/D6 70 L10 Vss Vss 71 N11 D7 PE7/D7 72 N12 Vcc Vcc 73 M13 N13 L12 D10 ...
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Section 1 Overview Pin No. LQFP- LGA- 144 145 Mode Mode E13 EXTAL EXTAL 98 F11 Vcc Vcc 99 D12 Vcc Vcc 100 G11 NC NC 101 E12 NC NC 102 E11 Vss Vss ...
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Pin No. LQFP- LGA- 144 145 Mode Mode 2 * 125 A8 P94/AN12/DA2 P94/AN12/DA2 126 D8 P95/AN13/DA3 P95/AN13/DA3 127 D7 P96/AN14/ P96/AN14/ DA4 * 3 DA4 * 128 D6 P97/AN15/ P97/AN15/ DA5 * DA5 * 3 129 ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) Power V 4, 41, 72, CC supply 98 10, 18, SS 25, 50, 70, 95, 102 ...
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H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) Clock XTAL 96 EXTAL 97 φ 94 SDRAMφ Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2378R H8S/2375 0.18μm H8S/2373 F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O ...
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Section 1 Overview H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) Operating MD2 1, 144, mode MD1 143 control MD0 DCTL * 1 62 RES System 92 control STBY 103 Rev.7.00 Mar. 18, 2009 page 20 of ...
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H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) System EMLE 32 control Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2378R H8S/2375 0.18μm H8S/2373 F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I Rev.7.00 Mar. 18, 2009 ...
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Section 1 Overview H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) Address A23 26, bus Data bus D15 73, 71, ...
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H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) HWR Bus 88 control LWR 87 BREQ 132 BREQO 130 BACK 131 Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2378R H8S/2375 0.18μm H8S/2373 F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R ...
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Section 1 Overview H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) UCAS Bus 85 control LCAS 86 DQMU * 1 85 DQML * 1 86 Rev.7.00 Mar. 18, 2009 page 24 of 1136 REJ09B0109-0700 Pin No. H8S/2378 ...
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H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) RAS/ Bus 109, 110, RAS2 control 35, 36 RAS3 to RAS5 RAS * 1 109 CAS * 1 110 WAIT 84 Pin No. H8S/2378 0.18μm ...
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Section 1 Overview H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) OE Bus 38, control (OE) 137 CKE * 1 38, (CKE 137 Interrupt NMI 40 signals IRQ15 to 86, 85, IRQ0 106 to 104, ...
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H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) DREQ1 DMA 82, DREQ0 controller 81 (DMAC) TEND1 104, TEND0 83 DACK1 106, DACK0 105 EDREQ3, EXDMA 33, EDREQ2 controller 3 (EXDMAC ETEND3, 59, ETEND2 34 EDACK3, ...
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Section 1 Overview H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) 16-bit timer TCLKA 44, pulse TCLKB 45, unit (TPU) TCLKC 47, TCLKD 49 TIOCA0 42, TIOCB0 43, TIOCC0 44, TIOCD0 45 TIOCA1 46, TIOCB1 47 TIOCA2 ...
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H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) Program- PO15 42, mable PO0 pulse generator (PPG) 8-bit timer TMO0 105, (TMR) TMO1 106 TMCI0 83, TMCI1 104 TMRI0 82, TMRI1 81 ...
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Section 1 Overview H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144 bus SCL1 139, interface 2 SCL0 137 (IIC2) SDA1 140, SDA0 138 A/D AN15 to 128 to 113 converter AN0 ADTRG 136 D/A ...
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H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) A/D AV 111 CC converter, D/A converter AV 129 SS Vref 112 Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2378R H8S/2375 0.18μm H8S/2373 F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R ...
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Section 1 Overview H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) I/O ports P17 P10 P27 P20 P35 to 137 to 142 P30 P47 to 120 to 113 P40 ...
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H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group Type Symbol (LQFP-144) I/O ports PD7 PD0 PE7 to 71, PE0 PF7 to 94, PF0 PG6 to 132 to 130, PG0 110 ...
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Section 1 Overview Rev.7.00 Mar. 18, 2009 page 34 of 1136 REJ09B0109-0700 ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU ⎯ 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) ⎯ 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W) • Two CPU operating modes ⎯ Normal mode * ⎯ Advanced mode Note: * For this ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI’s ...
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Stack structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as ...
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Section 2 CPU 2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and ...
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Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...
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Bit Bit Name Initial Value 1 V Undefined 0 C Undefined 2.4.5 Initial Register Values Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the ...
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Section 2 CPU 2.5.1 General Register Data Formats Figure 2.9 shows the data formats of general registers. Data Type Register Number RnH 1-bit data RnL 1-bit data RnH 4-bit BCD data 4-bit BCD data RnL Byte data RnH Byte data ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn : General register General register General register R RnH : General register RH RnL ...
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...
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Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP * , PUSH * LDM, STM MOVFPE ...
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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register ...
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Table 2.3 Data Transfer Instructions Size * Instruction Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions 1 Instruction Size * Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data ...
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Instruction Size * Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → ...
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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size * Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. ...
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Table 2.7 Bit Manipulation Instructions Instruction Size * Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Section 2 CPU Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ...
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Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...
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Section 2 CPU Table 2.9 System Control Instructions Size * Instruction Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR ...
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Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — else next ≠ 0 then EEPMOV.W — else next: Transfers a data block. Starting from the address set in ER5, transfers data ...
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Section 2 CPU (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 ...
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Table 2.11 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory indirect 2.7.1 Register ...
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Section 2 CPU Register Indirect with Pre-Decrement—@-ERn: The value subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The ...
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Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated ...
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Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table ...
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Addressing Mode and Instruction Format Absolute address Immediate Effective Address Calculation PC contents Sign extension Memory contents Memory contents Rev.7.00 Mar. 18, 2009 page 67 of 1136 Section 2 CPU Effective Address (EA) Sign extension Operand is immediate data. REJ09B0109-0700 ...
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Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this ...
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Bus-released state Exception handling state RES = High Reset state * 1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made ...
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Section 2 CPU Rev.7.00 Mar. 18, 2009 page 70 of 1136 REJ09B0109-0700 ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group have six operating modes (modes and 7). The H8S/2377 and H8S/2377R have five operating modes (modes 1 to ...
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Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of this ...
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H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group Bit Bit Name Initial Value ⎯ All 1 ⎯ All 0 3 FLSHE 0 ⎯ ⎯ 1 EXPE 0 RAME 1 Section 3 MCU ...
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Section 3 MCU Operating Modes • H8S/2377, H8S/2377R, H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R Bit Bit Name Initial Value ⎯ All 1 ⎯ All 0 3 FLSHE 0 ⎯ ⎯ 1 EXPE 0 RAME 1 ...
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Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, ports D and E function as a ...
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Section 3 MCU Operating Modes In the flash memory version, user program mode is entered by setting the SWE bit of FLMCR1 to 1. 3.3.5 Mode 5 This mode is a user boot mode of the flash memory. This mode ...
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Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Port Mode 1 * Port A PA7 to PA5 P /A PA4 to PA0 A Port B A Port ...
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Section 3 MCU Operating Modes 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.17 show memory maps for each product. (Expanded mode with on-chip ROM disabled) H'000000 H'FF4000 H'FFC000 H'FFD000 External address space H'FFFC00 Internal I/O registers H'FFFF00 ...
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ROM: 512 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'080000 External address space H'FF4000 On-chip RAM/ external address space * 1 H'FFC000 Reserved area * 4 H'FFD000 External address space H'FFFC00 Internal ...
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Section 3 MCU Operating Modes H'000000 H'FF4000 H'FF6000 H'FFC000 H'FFC800 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR When EXPE = 1, external ...
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ROM: 384 kbytes RAM: 24 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'060000 External address space H'FF4000 Reserved area * H'FF6000 On-chip RAM/ external address space * H'FFC000 Reserved area * H'FFC800 External address space ...
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Section 3 MCU Operating Modes H'000000 H'FF4000 H'FF8000 H'FFC000 H'FFC800 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF Notes: 1. This area is specified as external address space by clearing the RAME bit in SYSCR reserved area should not be ...
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ROM enabled) H'000000 H'040000 H'060000 H'FF4000 H'FF8000 H'FFC000 H'FFC800 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF Notes: 1. When EXPE = 1, external address space; when EXPE = 0, reserved area. 2. When EXPE = 1, external address space with RAME ...
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Section 3 MCU Operating Modes RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address H'FF4000 On-chip RAM/ external address H'FFC000 Reserved area * H'FFD000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External ...
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ROM: 384 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'060000 Reserved area * 4 H'080000 External address space H'FF4000 On-chip RAM/ external address space * 1 H'FFC000 Reserved area * 4 H'FFD000 ...
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Section 3 MCU Operating Modes Notes: 1. This area is specified as external address space by clearing the RAME bit in SYSCR reserved area should not be accessed. Figure 3.9 Memory Map for H8S/2373 and H8S/2373R ...
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RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF4000 On-chip RAM/ external address space * H'FFC000 Reserved area * H'FFD000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space ...
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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area* 4 H'080000 External address space H'FF4000 On-chip RAM/ external address space * 1 H'FFC000 Reserved ...
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RAM: 24 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF4000 Reserved area * H'FF6000 On-chip RAM/ external address space * H'FFC000 Reserved area * H'FFD000 External address space H'FFFC00 Internal I/O registers ...
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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 24 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area* 4 H'080000 External address space H'FF4000 Reserved area * 4 H'FF6000 On-chip RAM/ external address ...
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RAM: 16 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF4000 Reserved area * H'FF8000 On-chip RAM/ external address space * H'FFC000 Reserved area * H'FFD000 External address space H'FFFC00 Internal I/O registers ...
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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 16 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area* 4 H'080000 External address space H'FF4000 Reserved area * 4 H'FF8000 On-chip RAM/ external address ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more ...
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Section 4 Exception Handling Table 4.2 Exception Handling Vector Table Exception Source Power-on reset 3 Manual reset * Reserved for system use Trace 3 Interrupt (direct transition) * Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved for system use ...
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Exception Source External interrupt IRQ13 IRQ14 IRQ15 4 Internal interrupt * Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. Not available in this LSI reserved for system use. 4. For details ...
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Section 4 Exception Handling φ RES Internal address bus Internal read signal Internal write signal Internal data bus (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start ...
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RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * ...
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Section 4 Exception Handling 4.4 Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, ...
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Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. ...
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Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes (b) Advanced Modes Notes: 1. Ignored on return. 2. Normal modes ...
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Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack ...
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Section 4 Exception Handling Rev.7.00 Mar. 18, 2009 page 102 of 1136 REJ09B0109-0700 ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An ...
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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 INTCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISR ITSR SSIER Internal interrupt sources SWDTEND to IICI1 Interrupt ...
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Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ15 to IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value 7, 6 — All 0 5 INTM1 0 4 INTM0 0 3 NMIEG 0 ...
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Bit Bit Name Initial Value 15 — IPR14 1 13 IPR13 1 12 IPR12 1 11 — IPR10 1 9 IPR9 1 8 IPR8 1 7 — IPR6 1 5 IPR5 1 4 IPR4 ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value 3 — IPR2 1 1 IPR1 1 0 IPR0 1 5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit Bit Name ...
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Bit Bit Name Initial Value 10 IRQ10E 0 9 IRQ9E 0 8 IRQ8E 0 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E 0 R/W Description ...
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Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0. • ISCRH Bit Bit Name Initial Value 15 IRQ15SCB 0 14 IRQ15SCA ...
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Bit Bit Name Initial Value 9 IRQ12SCB 0 8 IRQ12SCA 0 7 IRQ11SCB 0 6 IRQ11SCA 0 5 IRQ10SCB 0 4 IRQ10SCA 0 R/W Description R/W IRQ12 Sense Control B R/W IRQ12 Sense Control A 00: Interrupt request generated at ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value 3 IRQ9SCB 0 2 IRQ9SCA 0 1 IRQ8SCB 0 0 IRQ8SCA 0 Rev.7.00 Mar. 18, 2009 page 112 of 1136 REJ09B0109-0700 R/W Description R/W IRQ9 Sense Control B R/W IRQ9 Sense ...
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ISCRL Bit Bit Name Initial Value 15 IRQ7SCB 0 14 IRQ7SCA 0 13 IRQ6SCB 0 12 IRQ6SCA 0 11 IRQ5SCB 0 10 IRQ5SCA 0 R/W Description R/W IRQ7 Sense Control B R/W IRQ7 Sense Control A 00: Interrupt request ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value 9 IRQ4SCB 0 8 IRQ4SCA 0 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 Rev.7.00 Mar. 18, 2009 page 114 of 1136 REJ09B0109-0700 R/W Description R/W IRQ4 ...
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Bit Bit Name Initial Value 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 R/W Description R/W IRQ1 Sense Control B R/W IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt ...
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Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit Bit Name Initial Value 15 IRQ15F 0 14 IRQ14F 0 13 IRQ13F 0 12 IRQ12F 0 11 IRQ11F 0 10 ...
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IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ15 to IRQ0. Bit Bit Name Initial Value 15 ITS15 0 14 ITS14 0 13 ITS13 0 12 ITS12 0 11 ITS11 0 10 ITS10 0 9 ITS9 0 8 ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value 6 ITS6 0 5 ITS5 0 4 ITS4 0 3 ITS3 0 2 ITS2 0 1 ITS1 0 0 ITS0 0 Rev.7.00 Mar. 18, 2009 page 118 of 1136 REJ09B0109-0700 R/W ...
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Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit Bit Name Initial Value 15 SSI15 0 14 SSI14 0 13 SSI13 0 12 SSI12 0 11 SSI11 ...
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Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to restore the chip from software standby mode. NMI Interrupt: Nonmaskable interrupt request (NMI) is ...
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IRQnSCA, IRQnSCB Edge/ level detection circuit IRQn input Note Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: • ...
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Section 5 Interrupt Controller Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Vector Source Source Number External pin NMI 7 IRQ0 16 IRQ1 17 IRQ2 18 IRQ3 19 IRQ4 20 IRQ5 21 IRQ6 22 IRQ7 ...
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Origin of Interrupt Interrupt Vector Source Source Number TPU_0 TGI0A 40 TGI0B 41 TGI0C 42 TGI0D 43 TCI0V 44 Reserved for 45 system use 46 47 TPU_1 TGI1A 48 TGI1B 49 TCI1V 50 TCI1U 51 TPU_2 TGI2A 52 TGI2B 53 ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number TPU_4 TGI4A 64 TGI4B 65 TCI4V 66 TCI4U 67 TPU_5 TGI5A 68 TGI5B 69 TCI5V 70 TCI5U 71 TMR_0 CMIA0 72 CMIB0 73 OVI0 74 Reserved for 75 ...
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Origin of Interrupt Interrupt Vector Source Source Number SCI_0 ERI0 88 RXI0 89 TXI0 90 TEI0 91 SCI_1 ERI1 92 RXI1 93 TXI1 94 TEI1 95 SCI_2 ERI2 96 RXI2 97 TXI2 98 TEI2 99 SCI_3 ERI3 100 RXI3 101 ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number IIC2 IICI0 116 Reserved for 117 system use IICI1 118 Reserved for 119 system use Reserved for 120 system use 121 122 123 124 125 126 127 Notes: ...
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Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table ...
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Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure ...
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Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level ( bits) in the CPU and the IPR ...
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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is ...
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Figure 5.5 Interrupt Exception Handling Rev.7.00 Mar. 18, 2009 page 131 of 1136 Section 5 Interrupt Controller REJ09B0109-0700 ...
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Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in ...