YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 819

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

falling edge of the start bit using the basic clock, and performs internal synchronization. As shown
in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th
pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given
by the following formula.
Where M: Reception margin (%)
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = ⏐ (0.5 –
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode
2N
1
186 clocks
0
) – (L – 0.5) F –
(Using Clock of 372 Times the Bit Rate)
185
372 clocks
Start bit
371
Section 15 Serial Communication Interface (SCI, IrDA)
⏐D – 0.5⏐
0
N
D0
Rev.7.00 Mar. 18, 2009 page 751 of 1136
(1 + F) ⏐ × 100 [%]
185
371 0
REJ09B0109-0700
D1