YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 471

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EDREQ Pin Falling Edge Activation Timing: Figure 8.26 shows an example of single address
mode transfer activated by the EDREQ pin falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the DMA single cycle, acceptance resumes
after the end of the single cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle start; EDREQ pin high level sampling is started at rise of φ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of single cycle.
Figure 8.26 Example of Single Address Mode Transfer Activated by EDREQ Pin Falling
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
φ
EDREQ
Address bus
EDACK
DMA control
Channel
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
clearance period
Single
[3]
Request
DMA single
Transfer source/
destination
Edge
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
Rev.7.00 Mar. 18, 2009 page 403 of 1136
Section 8 EXDMA Controller (EXDMAC)
[5]
clearance period
Single
[6]
Request
Transfer source/
DMA single Bus release
destination
Idle
Acceptance
resumed
[7]
REJ09B0109-0700