YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 609

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
7 to 4
Notes: 1. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and H8S/2373.
3
2
1
0
2. When synchronous DRAM interface is not used, input a low-level signal on the DCTL pin.
3. Only modes 1 and 2 are supported on ROM-less versions.
Bit Name
—
PH3DDR
PH2DDR
PH1DDR
PH0DDR
Initial Value
All 0
0
0
0
0
R/W
—
W
W
W
W
Description
Reserved
• Modes 1 *
• Mode 7 (when EXPE = 0)
When the OE output enable bit (OEE) and OE output select bit (OES) are
set to 1, pin PH3 functions as the OE output pin. Otherwise, when bit
CS7E is set to 1, pin PH3 functions as a CS output pin when the
corresponding PH3DDR bit is set to 1, and as an input port when the bit is
cleared to 0. When bit CS7E is cleared to 0, pin PH3 is an I/O port, and its
function can be switched with PH3DDR. When areas 2 to 5 are specified
as continuous synchronous DRAM space *
When bit CS6E is set to 1, setting bit PH2DDR makes pin PH2 function as
the CS6 output pin and as an I/O port when the bit is cleared to 0. When
bit CS6E is cleared to 0, pin PH2 is an I/O port, and its function can be
switched with PH2DDR.
Pin PH1 functions as the SDRAMφ *
DCTL pin *
input level of the DCTL pin *
and bit PH1DDR is set to 1; if the bit is cleared to 0, pin PH1 functions as
an I/O port. When bit CS5E is cleared to 0, pin PH1 is an I/O port, and its
function can be switched with PH1DDR. When area 5 is specified as
DRAM space and bit CS5E is set to 1, pin PH1 functions as the RAS5
output pin and as an I/O port when the bit is cleared to 0.
Pin PH0 functions as the CS4 output pin when area 4 is specified as
normal space and bit PH0DDR is set to 1; if the bit is cleared to 0, pin
PH0 functions as an I/O port. When bit CS4E is cleared to 0, pin PH0 is
an I/O port, and its function can be switched with PH0DDR. When area 4
is specified as DRAM space and bit CS5E is set to 1, pin PH0 functions
as the RAS4 output pin and as an I/O port when the bit is cleared to 0.
When areas 2 to 5 are specified as continuous synchronous DRAM *
PH0 functions as the WE output pin and as an I/O port when the bit is
cleared to 0.
Pins PH3 to PH0 are I/O ports, and their functions can be switched with
PHDDR.
Pin PH1 functions as the SDRAMφ *
DCTL pin *
PH1 is an I/O port and its function can be switched with PHDDR.
3
, 2 *
2
2
is high. Pin PH1 functions as the CS5 output pin when the
is high. When the input level of the DCTL pin *
3
, 4 and 7 (when EXPE = 1)
Rev.7.00 Mar. 18, 2009 page 541 of 1136
2
is low, area 5 is specified as normal space,
1
1
output pin when the input level of the
output pin when the input level of the
1
, OE output is CKE output.
Section 10 I/O Ports
REJ09B0109-0700
2
is low, pin
2
, pin