YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 208

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 140 of 1136
REJ09B0109-0700
Name
Chip select 4/
row address strobe 4/
write enable *
Chip select 5/
row address strobe 5/
SDRAMφ *
Chip select 6
Chip select 7
Upper column address strobe/
upper data mask enable *
Lower column address strobe/
lower data mask enable *
Output enable/clock enable
Wait
Bus request
Bus request acknowledge
Bus request output
1
1
1
1
Symbol
CS4/
RAS4/
WE *
CS5/
RAS5/
SDRAMφ *
CS6
CS7
UCAS/
DQMU *
LCAS/
DQML *
OE/
CKE *
WAIT
BREQ
BACK
BREQO
1
1
1
1
1
I/O
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Function
Strobe signal indicating that area 4 is
selected, DRAM row address strobe signal
when area 4 is DRAM space, or write
enable signal of the synchronous DRAM
when the synchronous DRAM interface is
selected.
Strobe signal indicating that area 5 is
selected, DRAM row address strobe signal
when area 5 is DRAM space, or dedicated
clock signal for the synchronous DRAM
when the synchronous DRAM interface is
selected.
Strobe signal indicating that area 6 is
selected.
Strobe signal indicating that area 7 is
selected.
16-bit DRAM space upper column address
strobe signal, 8-bit DRAM space column
address strobe signal, upper data mask
signal of 16-bit synchronous DRAM space,
or data mask signal of 8-bit synchronous
DRAM space.
16-bit DRAM space lower column address
strobe signal or lower data mask signal for
the 16-bit synchronous DRAM space.
Output enable signal for the DRAM space
or clock enable signal for the synchronous
DRAM space.
Wait request signal when accessing
external address space.
Request signal for release of bus to
external bus master.
Acknowledge signal indicating that bus has
been released to external bus master.
External bus request signal used when
internal bus master accesses external
address space when external bus is
released.